EP0316876A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A digital signal receiving circuit with means for controlling a baud rate sampling phase by a power of sampled signals
Assignee: NEC Corp
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Filing: 1988-11-15
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Granted: —
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Expires: 2008-11-15
Abstract
Abstract In a baud rate sampling type receiving circuit for use in a system for transmitting digital data signal at a transmission baud rate, in order to control the sampling phase at the optimum phase, desired elements of an autocorrelation function of a series of baud rate sampled signals are calculated and are linearly summed by a calculating circuit (16) to provide a linear summation as a power of the series of sampled signals. The sampling phase at the baud rate sampling is controlled by a control circuit (17) by use of the linear summation so that the power is maximized, whereby the sampling phase is maintained at the optimum sampling phase.
Inventors
- 👤 Masanobu C/O Nec Corporation Arai
- 👤 Masaru C/O Nec Corporation Yamaguchi
- 👤 Takenori C/O Nec Miyagi Ltd. Ogata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:00
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/02; H04L7/033; H04L7/0334
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
121 words
In a receiving circuit for use in a transmission system of a digital signal at a transmission baud rate, said receiving circuit comprising a baud rate sampling circuit for sampling said digital signal as a received signal by a sampling signal of a sampling rate equal to said transmission baud rate to produce a series of sampled signals, wherein the improvement comprises: calculating means coupled with said baud rate sampling circuit for calculating a linear summation of predetermined elements of an autocorrelation function of said series of sampled signals as a power of said series of sampled signals; and sampling control means responsive to said power for controlling a sampling phase of said sampling signal so that said power is maximized.
Claim 2
Dependent Claim
121 words
In a receiving circuit for use in a transmission system of a digital signal at a transmission baud rate, said receiving circuit comprising a baud rate sampling circuit for sampling said digital signal as a received signal by a sampling signal of a sampling rate equal to said transmission baud rate to produce a series of sampled signals, wherein the improvement comprises: calculating means coupled with said baud rate sampling circuit for calculating a linear summation of predetermined elements of an autocorrelation function of said series of sampled signals as a power of said series of sampled signals; and sampling control means responsive to said power for controlling a sampling phase of said sampling signal so that said power is maximized.
Claim 3
Dependent Claim
27 words
A receiving circuit as claimed in Claim 1, which further comprises a digital filter for filtering and delivering said series of sampled signals to said calculating means.
Claim 4
Dependent Claim
20 words
A receiving circuit as claimed in Claim 2, wherein said digital filter has a filtering characteristic of (1 - D).
Claim 5
Dependent Claim
76 words
A receiving circuit as claimed in any of Claims 1 to 3 wherein said calculating means comprises first means for calculating said predetermined elements of the autocorrelation function of said series of sampled signals to produce calculated data signals, second means for summing said calculated data signal to produce a summed data signal, and third means for integrating said summed data signal for a predetermined time period to produce an integrated signal as said linear summation.
Claim 6
Dependent Claim
83 words
A receiving circuit as claimed in Claim 4, wherein said first means comprises a predetermined number of delay means each having a delaying time equal to a sampling period corresponding to said sampling rate and being connected in a cascade for delaying said series of sampled signals, each delay means delivering delayed signals, and a plurality of multiplying means coupled with said delay means, respectivley, to multiply said delayed signals by said series of sampled signals to produce said calculated data signals, respectivley.
Claim 7
Dependent Claim
58 words
A receiving circuit as claimed in Claim 4 or 5 wherein said third means comprises adder means for adding said summed data signal and an adding signal to produce an added signal, and delaying means for delaying said added signal to produce said integrated signal, said integrated signal being supplied to said adder means as said adding signal.
Claim 8
Dependent Claim
70 words
A receiving circuit as claimed in any of Claims 1 to 6 wherein said calculating means comprises a read only memory for memorizing a program for calculating said linear summation, a random access memory for storing said series of the sampled signals, and processing means for executing said calculating program to produce said linear summation as said power in cooperation with said read only memory and said random access memory.
References Cited (Backward Citations)
No citation records indexed.
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