A DRAM cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof

Claim 2

A semiconductor memory device having a memory cell comprising a transistor stacked on a capacitor thereof, a word line and a bit line, said semiconductor memory device comprising: (a) a first insulating layer formed on a semiconductor substrate; (b) a semiconductor pillar structure formed on said first insulating layer, arranged in a matrix array, and isolated by a trench extending to said first insulating layer, said pillar structure comprising a first semiconductor layer of a first conductivity type formed on said first insulating layer, a second semiconductor layer of a second conductivity type opposite to the first conductivity type formed on said first semiconductor layer, and a third semiconductor layer of the first conductivity type formed on said second semiconductor layer, and said transistor being formed in an upper portion of the pillar structure and said capacitor being formed in a lower portion of the pillar structure; (c) a second insulating layer formed over a side surface of said pillar structure having a first and second regions, the first region being used as an insulating layer of said capacitor and the second region being used as a gate insulating layer of said transistor; (d) a first conductive layer for forming a cell plate of said capacitor, formed in said trench and on said first insulating layer, said first conductive layer having substantially the same thickness as the first semiconductor layer of said pillar structure and sandwiching the first region of said second insulating layer with said first semiconductor layer; (e) a third insulating layer formed on said first conductive layer; (f) a second conductive layer formed over said third insulating layer and the second region of said second insulating layer, and said second conductive layer surrounding said second semiconductor layer of said pillar structure and forming a gate electrode of said transistor, separated from adjacent second conductive layers in a first direction and connected with adjacent second conductive layers in a second direction different from the first direction, so as to form said word line; and (g) a third conductive layer formed on said third semiconductor layer and connected with adjacent third semiconductor layers of said pillar structure along the first direction so as to form said bit line.

Claim 3

A semiconductor memory device having a memory cell according to claim 1, wherein said second semiconductor layer of the second conductivity type comprises two layers, a lower second semiconductor layer having a low impurity concentration and an upper second semiconductor layer having a high impurity concentration.

Claim 4

A semiconductor memory device having a memory cell according to claim 2, wherein the impurity concentration of the lower second semiconductor layer is about a tenth of that of the upper second semiconductor layer.

Claim 5

A semiconductor memory device having a memory cell according to claim 2 or 3, wherein a surface level of said first conductive layer is within a height range of the lower second semiconductor layer of said second semiconductor layer.

Claim 6

A semiconductor memory device having a memory cell comprising a transistor stacked on a capacitor thereof, a word line and a bit line, said semiconductor memory device comprising: (a) a first insulating layer formed on a semiconductor substrate; (b) a semiconductor pillar structure formed on said first insulating layer, arranged in a matrix array, and isolated by a trench extending to said first insulating layer, said pillar structure comprising a first semiconductor layer of a second conductivity type of a low impurity concentration formed on said first insulating layer, a second semiconductor layer of the second conductivity type of a high impurity concentration formed on said first semiconductor layer, and a third semiconductor layer of a first conductivity type opposite to the second conductivity type formed on said second semiconductor layer, and said transistor being formed in an upper portion of the pillar structure and said capacitor being formed in a lower portion of the pillar structure; (c) a second insulating layer formed over a side surface of said pillar structure having a first and second regions, the first region being used as an insulating layer of said capacitor and the second region being used as a gate insulating layer of said transistor; (d) a first conductive layer for forming a cell plate of said capacitor, formed in said trench and on said first insulating layer, said first conductive layer having substantially the same thickness as the first semiconductor layer of said pillar structure and sandwiching the first region of said second insulating layer with said first semiconductor layer; (e) a third insulating layer formed on said first conductive layer; (f) a second conductive layer formed over said third insulating layer and the second region of said second insulating layer, and said second conductive layer surrounding said second semiconductor layer of said pillar structure and forming a gate electrode of said transistor, separated from adjacent second conductive layers in a first direction and connected with adjacent second conductive layers in a second direction different from the first direction, so as to form said word line; and (g) a third conductive layer formed on said third semiconductor layer and connected with adjacent third semiconductor layers of said pillar structure along the first direction so as to form said bit line.

Claim 7

A semiconductor memory device having a memory cell comprising a transistor stacked on a capacitor thereof, a word line and a bit line, said semiconductor memory device comprising: (a) a first insulating layer formed on a semiconductor substrate; (b) a semiconductor pillar structure formed on said first insulating layer, arranged in a matrix array, and isolated by a trench extending to said first insulating layer, said pillar structure comprising a first semiconductor layer of a second conductivity type of a low impurity concentration formed on said first insulating layer, a second semiconductor layer of the second conductivity type of a high impurity concentration formed on said first semiconductor layer, and a third semiconductor layer of a first conductivity type opposite to the second conductivity type formed on said second semiconductor layer, and said transistor being formed in an upper portion of the pillar structure and said capacitor being formed in a lower portion of the pillar structure; (c) a second insulating layer formed over a side surface of said pillar structure having a first and second regions, the first region being used as an insulating layer of said capacitor and the second region being used as a gate insulating layer of said transistor; (d) a first conductive layer for forming a cell plate of said capacitor, formed in said trench and on said first insulating layer, said first conductive layer having substantially the same thickness as the first semiconductor layer of said pillar structure and sandwiching the first region of said second insulating layer with said first semiconductor layer; (e) a third insulating layer formed on said first conductive layer; (f) a second conductive layer formed over said third insulating layer and the second region of said second insulating layer, and said second conductive layer surrounding said second semiconductor layer of said pillar structure and forming a gate electrode of said transistor, separated from adjacent second conductive layers in a first direction and connected with adjacent second conductive layers in a second direction different from the first direction, so as to form said word line; and (g) a third conductive layer formed on said third semiconductor layer and connected with adjacent third semiconductor layers of said pillar structure along the first direction so as to form said bit line.

Claim 8

A semiconductor memory device having a memory cell according to claim 5, wherein said semiconductor substrate is of the second conductivity type and a hole is formed in said first insulating layer under said pillar structure and said first semiconductor layer contacts with the substrate through said hole.

Claim 9

A semiconductor memory device having a memory cell according to any of the preceding claims, wherein said semiconductor pillar structure is arranged in the matrix array having a gap between the pillars in the first direction of greater than that in the second direction.

Claim 10

A semiconductor memory device having a memory cell according to any of the preceding claims, wherein said second conductive layer is of doped polysilicon and has a curved surface having a gradually decreasing thickness with a height in cross section.

Claim 11

A semiconductor memory device having a memory cell comprising a transistor stacked on a capacitor thereof formed in a semiconductor pillar and buried layers surrounding said semiconductor pillar, said memory device comprising: (a) a semiconductor substrate; (b) an insulating layer formed on said semiconductor substrate; (c) said semiconductor pillar comprising a plurality of semiconductor layers formed on said insulating layer and a plurality of said semiconductor pillars arranged in a matrix array in rectangular coordinates, a circumferential sides of the semiconductor pillar being covered with an insulating film, and said semiconductor pillar comprising a layer forming a storage electrode as a first electrode of said capacitor on said insulating layer and vertical layers forming active regions of the transistor formed on said storage electrode; (d) said buried layers comprising a layer forming a cell plate on said insulating layer, surrounding said storage electrode and having a height substantially equal to that of the storage electrode and forming a second electrode of the capacitor, and said buried layers further comprising a layer forming a gate electrode above said cell plate, surrounding a channel region of said active regions of the transistor, said gate electrode arranged in the Y-direction of rectangular coordinates being connected with each other and forming a word line; and (e) a bit line connecting a plurality of top regions of said active region of the transistor in the X-direction of the rectangular coordinates.

Claim 12

A semiconductor memory device having a memory cell comprising a transistor stacked on a capacitor thereof formed in a semiconductor pillar and buried layers surrounding said semiconductor pillar, said memory device comprising: (a) a semiconductor substrate; (b) an insulating layer formed on said semiconductor substrate; (c) said semiconductor pillar comprising a plurality of semiconductor layers formed on said insulating layer and a plurality of said semiconductor pillars arranged in a matrix array in rectangular coordinates, a circumferential sides of the semiconductor pillar being covered with an insulating film, and said semiconductor pillar comprising a layer forming a storage electrode as a first electrode of said capacitor on said insulating layer and vertical layers forming active regions of the transistor formed on said storage electrode; (d) said buried layers comprising a layer forming a cell plate on said insulating layer, surrounding said storage electrode and having a height substantially equal to that of the storage electrode and forming a second electrode of the capacitor, and said buried layers further comprising a layer forming a gate electrode above said cell plate, surrounding a channel region of said active regions of the transistor, said gate electrode arranged in the Y-direction of rectangular coordinates being connected with each other and forming a word line; and (e) a bit line connecting a plurality of top regions of said active region of the transistor in the X-direction of the rectangular coordinates.

Claim 15

A method of manufacturing a semiconductor memory device having a memory cell according to claim 10, wherein said step (a) of providing a substrate further comprises the following substeps of: bringing two semiconductor substrates together, a silicon oxide layer being formed at least on one of substrates, and applying an electrical attracting force between said two substrates in a heated atmosphere, thereby said one of the substrates and the silicon dioxide layer respectively being used as said base substrate and said silicon dioxide layer in the step (a).

Claim 16

A method of manufacturing a semiconductor memory device having a memory cell according to claim 10 or 11, wherein said step (b) of forming a semiconductor pillar comprises a condition that the gap between adjacent semiconductor pillars in the first direction of the rectangular coordinates is greater than that in the second direction.