EP0315385A2
Expired / Lapsed
EP
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Delay circuits for integrated circuits
Assignee: Sony Corp
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Filing: 1988-10-28
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Granted: —
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Expires: 2008-10-28
Abstract
Abstract A delay circuit includes a current mirror circuit having a pair of MOS transistors (11, 12), a constant current source (14) and a capacitance (16). The delay time of the circuit is determined by the charging time of the capacitance (16) connected to one (12) of the MOS transistors. A stable delay time may be obtained despite manufacturing fluctuations, and the occupation area of the circuit may be reduced.
Inventors
- 👤 Hideki C/O Patents Division Usuki
- 👤 Shumpei C/O Patents Division Kohri
- 👤 Masatoshi C/O Patents Division Yano
- 👤 Hiroshi C/O Patents Division Ishida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 23:20
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
101 words
A delay circuit for producing a predetermined delay time for an integrated circuit, the delay circuit comprising: a current mirror circuit including at least a pair of current mirror connected MOS transistors (11, 12; 21, 22); a constant current source (14; 24) connected to one (11; 21) of the MOS transistors; and a capacitance (16; 26) connected to the other (12; 22) of the MOS transistors, so as to be charged by the current flowing in the other MOS transistor (12; 22); whereby the delay time of the delay circuit is determined by the charging time of the capacitance (16; 26).
Claim 2
Dependent Claim
101 words
A delay circuit for producing a predetermined delay time for an integrated circuit, the delay circuit comprising: a current mirror circuit including at least a pair of current mirror connected MOS transistors (11, 12; 21, 22); a constant current source (14; 24) connected to one (11; 21) of the MOS transistors; and a capacitance (16; 26) connected to the other (12; 22) of the MOS transistors, so as to be charged by the current flowing in the other MOS transistor (12; 22); whereby the delay time of the delay circuit is determined by the charging time of the capacitance (16; 26).
Claim 3
Dependent Claim
30 words
A delay circuit according to claim 1, wherein each MOS transistor is a PMOS transistor (11, 12; 21, 22), and the gates of both PMOS transistors are connected in common.
Claim 4
Dependent Claim
31 words
A delay circuit according to claim 1 or claim 2, wherein the constant current source is a PMOS transistor (14) to the gate of which an input signal may be supplied.
Claim 5
Dependent Claim
35 words
A delay circuit according to claim 1 or claim 2, wherein the constant current source is an NMOS transistor (24) to the gate of which an input signal may be supplied through an inverter (29).
Claim 6
Dependent Claim
31 words
A delay circuit according to any one of the preceding claims, comprising means (15; 25) for discharging the capacitance (16; 26), wherein the discharging means is switched by an input signal.
Claim 7
Dependent Claim
25 words
A delay circuit according to claim 5, wherein the discharging means is an NMOS transistor (15; 25) connected in parallel with the capacitance (16; 26).
Claim 8
Dependent Claim
20 words
A delay circuit according to any one of the preceding claims, wherein the capacitance (16; 26) is an MOS capacitor.
Claim 9
Dependent Claim
32 words
A delay circuit according to any one of the preceding claims, wherein the current capability of one of the MOS transistors (11, 12; 21, 22) is different from that of the other.
References Cited (Backward Citations)
No citation records indexed.
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