EP0315157A2
Expired / Lapsed
EP
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Semiconductor memory system
Assignee: Toshiba Corp
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Filing: 1988-11-02
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Granted: —
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Expires: 2008-11-02
Abstract
Abstract In a semiconductor memory system of the serial column access type, a redundant column (55) is used for replacing a defective column. Redundant data lines (SD, SD ) are connected to the redundant column (55) through a redundant column selection gate (15). A defective address detection circuit (43) detects the address of a defective column to enable the redundant column selection gate. An address counter (42) is provided for a defective address detection circuit (43). A redundant column selection circuit (25) selects the redundant column in response to a detection signal from the defective address detection circuit (43). A data line switching circuit (41) switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines (D, D ) to the redundant data lines (SD, SD ). With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit (21₁ to 21n) operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.
Inventors
- 👤 Hiroshi C/O Patent Division Sahara
- 👤 Haruki C/O Patent Division Toda
- 👤 Shigeo C/O Patent Division Ohshima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 19:32
CPC Classifications
G; G11; G11C; G11C7/00; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/846
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A semiconductor memory system of the serial column access type characterized by comprising: "n" regular columns (51₁ to 51n), where "n" is a positive integer; "n" column selection gates (11₁ to 11n) provided respectively corresponding to said regular columns; regular data lines (D, D ) connected through said column selection gates (11₁ to 11n) respectively to said columns (51₁ to 51n); "n" column selection circuits (21₁ to 21n) respectively provided for said clumn selection gates; a redundant column (55) used for replacing a defective column; a redundant column selection gate (15) provided for said redundant column (55); redundant data lines (SD, SD ) connected to said redundant column (55) through said redundant column selection gate (15); a data input/output driver (31); a defective address detection means (42, 43, 25) for detecting the address of a defective column to select said redundant column; and a data line switching circuit (44, 41) for switching, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines (D, D ) to said redundant data lines (SD, SD ).
Claim 2
Dependent Claim
183 words
A semiconductor memory system of the serial column access type characterized by comprising: "n" regular columns (51₁ to 51n), where "n" is a positive integer; "n" column selection gates (11₁ to 11n) provided respectively corresponding to said regular columns; regular data lines (D, D ) connected through said column selection gates (11₁ to 11n) respectively to said columns (51₁ to 51n); "n" column selection circuits (21₁ to 21n) respectively provided for said clumn selection gates; a redundant column (55) used for replacing a defective column; a redundant column selection gate (15) provided for said redundant column (55); redundant data lines (SD, SD ) connected to said redundant column (55) through said redundant column selection gate (15); a data input/output driver (31); a defective address detection means (42, 43, 25) for detecting the address of a defective column to select said redundant column; and a data line switching circuit (44, 41) for switching, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines (D, D ) to said redundant data lines (SD, SD ).
Claim 3
Dependent Claim
22 words
A semiconductor memory system according to claim 1, characterized in that said column selection circuits (21₁ to 21n) comprise a shift register.
Claim 4
Dependent Claim
94 words
A semiconductor memory system according to claim 1, characterized in that said defective address detection means (42, 43, 25) includes an address counter (42) for monitoring the address data, a defective address detection circuit (43) for detecting a defective address from the output signal of the address counter, a redundant column selection circuit (25) for selecting a redundant column by driving said redundant column selection gate (15) in response to the signal from said defective address detection circuit (43), thereby to connect said redundant column to said redundant data lines (SD and SD ).
Claim 5
Dependent Claim
92 words
A semiconductor memory system according to claim 1, characterized in that said redundant data-line selection means (44, 41) includes a redundant data line selection circuit (44) for producing a redundant dataline selection signal in response to the signal from said defective address detection circuit (43), and a data-line switching circuit (41) for disconnecting, in response to the output signal of said redundant dataline selection circuit (44), said regular data lines from said input/output drive circuit (31), and for connecting said redundant data lines (SD, SD ) to said input/output drive circuit (31).
Claim 6
Dependent Claim
29 words
A semiconductor memory system according to claim 3, characterized by further comprising a start address set-up circuit (32) for setting up said column selection circuits and said address counter.
Claim 7
Dependent Claim
221 words
A semiconductor memory system of the serial column access type characterized by comprising: "n" regular columns (51₁ to 51n), where "n" is a positive integer; "n" column selection gates (11₁ to 11n) respectively provided corresponding to said regular columns; regular data lines (D, D ) connected through said column selection gates (11₁ to 11n) respectively to said columns (51₁ to 51n); "n" column selection circuits (21₁ to 21n) comprising a shift register, respectively provided for said column selection gates; a redundant column (55) used for replacing a defective column; redundant data lines (SD, SD ) connected to said redundant column (55) through a redundant column selection gate (15); a defective address detection circuit (43) for detecting the address of a defective column to enable said redundant column selection gate; an address counter (42) for said defective address detection circuit (43); a start address set-up circuit (32) for setting up said column selection circuits and said address counter; a redundant column selection circuit (25) for selecting said redundant column in response to a detection signal from said defective address detection circuit (43); and a data line switching means (41) for switching, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines (D, D ) to said redundant data lines (SD, SD ).
Claim 8
Dependent Claim
221 words
A semiconductor memory system of the serial column access type characterized by comprising: "n" regular columns (51₁ to 51n), where "n" is a positive integer; "n" column selection gates (11₁ to 11n) respectively provided corresponding to said regular columns; regular data lines (D, D ) connected through said column selection gates (11₁ to 11n) respectively to said columns (51₁ to 51n); "n" column selection circuits (21₁ to 21n) comprising a shift register, respectively provided for said column selection gates; a redundant column (55) used for replacing a defective column; redundant data lines (SD, SD ) connected to said redundant column (55) through a redundant column selection gate (15); a defective address detection circuit (43) for detecting the address of a defective column to enable said redundant column selection gate; an address counter (42) for said defective address detection circuit (43); a start address set-up circuit (32) for setting up said column selection circuits and said address counter; a redundant column selection circuit (25) for selecting said redundant column in response to a detection signal from said defective address detection circuit (43); and a data line switching means (41) for switching, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines (D, D ) to said redundant data lines (SD, SD ).
References Cited (Backward Citations)
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