EP0314034A2
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EP
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Logic operation circuit
Assignee: Fujitsu VLSI Ltd
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Filing: 1988-10-23
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Granted: —
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Expires: 2008-10-23
Abstract
Abstract A logic operation circuit includes an instruction signal generating circuit (11) for generating an instruction signal (X0 - X3) which designates a bit of a predetermined n-bit code signal (ø₀ - ø₃) in accordance with a combination of a first input logical numeral (S) and a second input logical numeral (D). The logic operation circuit also includes a bit selecting circuit (10) for selecting said bit designated by the instruction signal (X0 - X3) generated by the instruction signal generating circuit (11) and for outputting the selected bit as an output logical numeral (Q).
Inventors
- 👤 Hiroaki Ogawa
- 👤 Eisaku Itoh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
90 words
A logic operation circuit, characterized in that the logic operation circuit comprises instruction signal generating means (11) for generating an instruction signal (X0 - X3) which designates a bit of a predetermined n-bit code signal (ø₀ - ø₃) in accordance with a combination of a first input logical numeral (S) and a second input logical numeral (D); and bit selecting means (10) for selecting said bit designated by the instruction signal generated by the instruction signal generating means and for outputting the selected bit as an output logical numeral (Q).
Claim 2
Dependent Claim
90 words
A logic operation circuit, characterized in that the logic operation circuit comprises instruction signal generating means (11) for generating an instruction signal (X0 - X3) which designates a bit of a predetermined n-bit code signal (ø₀ - ø₃) in accordance with a combination of a first input logical numeral (S) and a second input logical numeral (D); and bit selecting means (10) for selecting said bit designated by the instruction signal generated by the instruction signal generating means and for outputting the selected bit as an output logical numeral (Q).
Claim 3
Dependent Claim
42 words
A logic operation circuit as claimed in claim 1, characterized in that the instruction signal generating means (11) comprises decoder means (11) for decoding the first and second input logical numerals (S, D) and producing the instruction signal which consists of n-bits.
Claim 4
Dependent Claim
71 words
A logic operation circuit as claimed in any of claims 1 and 2, characterized in that the bit selecting means (10) comprises n number of transfer gates (12 - 15) each having a control terminal (12a - 15a) to which the instruction signal (X0 - X3) is applied, and in that the transfer gates are turned ON/OFF depending on a level of the instruction signal applied to the respective control terminal.
Claim 5
Dependent Claim
69 words
A logic operation circuit as claimed in any of claims 1 to 3, characterized in that the bit selecting means (10) comprises n number of P-channel metal-oxide-semiconductor (MOS) transistors (22 - 25), and in that sources of the MOS transistors are supplied with respective bits of the n-bit code signal (ø₀ - ø₃), and drains of the MOS transistors are mutually connected and outputs the output logical numeral (Q).
Claim 6
Dependent Claim
65 words
A logic operation circuit as claimed in claim 4, characterized in that the instruction signal generating means (11) comprises n number of NAND gates (18 - 21), and input terminals of the NAND gates are supplied with the first and second input logical numerals (S, D), and output terminals of the NAND gates are connected to gates of the respective MOS transistors 22 - 25).
Claim 7
Dependent Claim
69 words
A logic operation circuit as claimed in any of claims 1 and 2, characterized in that the bit selecting means (10) comprises n number of N-channel metal-oxide-semiconductor (MOS) transistors (31 - 34), and in that drains of the MOS transistors are supplied with respective bits of the n-bit code signal (ø₀ - ø₃), and sources of the MOS transistors are mutually connected and outputs the output logical numeral (Q).
Claim 8
Dependent Claim
65 words
A logic operation circuit as claimed in claim 6, characterized in that the instruction signal generating means (11) comprises n number of NOR gates (27 - 30), and input terminals of the NAND gates are supplied with the first and second input logical numerals (S, D), and output terminals of the NOR gates are connected to gates of the respective MOS transistors (31 - 34).
Claim 9
Dependent Claim
36 words
A logic operation circuit as claimed in any of claims 1 to 7, characterized in that the first and second input logical numerals (S, D) are supplied to the instruction signal generating means (11) per bit.
Claim 10
Dependent Claim
29 words
A logic operation circuit as claimed in claim any of claims 1 to 8, characterized in that the first and second input logical numerals (S, D) are image data.
References Cited (Backward Citations)
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