Semiconductor chip package

Claim 2

A semiconductor chip package, characterized by: a) a plurality of programmable pads (26) located on an exterior surface of a semiconductor chip package, each pad being adapted for interconnection with a semiconductor chip; b) a plurality of signal connectors (22) located on an exterior surface of the package; c) a plurality of signal connections (30), each signal connection providing an electrically conductive path between an individual programmable pad (26) and a corresponding individual signal connector (22); d) a plurality of dedicated power or ground connectors located on an exterior surface of the package; and e) connection means (32) comprising conductive paths within the package for selectivly connecting any programmable pad (26) to a power or ground connector, any programmable pad so connected also remaining connected to a corresponding signal connector.

Claim 3

The apparatus of claim 1, characterized in that: a) the plurality of signal connections (30) comprises a plurality of signal leads configured on a signal lead layer (6, 9) located within the package; and b) the connection means (32 to 40) comprises: c) at least one first (34, 38) and second (36, 40) power or ground rings; and d) first (42, 46) and second (44, 48) power or ground planes, the first power or ground plane being connected for electrical conduction with the first power or ground ring, the second power or ground plane being connected for electrical conduction with the second power or ground ring, each dedicated power or ground connector being connected for electrical conduction with one of the first or second power or ground planes.

Claim 4

The apparatus of claim 2, characterized in that the connection means comprises power or ground pad connection means (28) for connecting selected programmable pads (26) to one of the power or ground rings (34 to 40) and for connecting other programmable pads to the other power or ground ring, the power or ground pad connection means comprising a plurality of power or ground pads (32) located in a single layer (2), each power or ground pad being configured and located for an electrically conductive connection between one selected programmable pad and one of the power or ground rings.

Claim 5

The apparatus of claim 3, characterized in that: the power or ground rings (34 - 40) are located in a layer (3) within the package; the layer (2) of powre or ground pads (32) is located within the package; and the power or ground pad connection means comprises vias (28) which provide electrically conductive paths between each power or ground pad, a corresponding programmable pad (26), and a corresponding power or ground ring (Fig. 1 to 3).

Claim 6

The apparatus of claim 2, characterized in that: the power or ground rings (34 to 40) are located on an exterior surface (Fig. 13).

Claim 7

The apparatus of claim 5, characterized in that the power or ground rings (34 to 40) are located on the same exterior surface as the programmable pads (26).

Claim 8

A semiconductor chip package, characterized by: a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer (6, 9); d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first and second power or ground rings (34 to 40); g) a plurality of power or ground pads (32) located in a layer (2) within the package, each power or ground pad being configured and located for connection by vias (28) with one selected programmable pad (26) and one of the power or ground rings; h) a plurality of power or ground pad vias (28): there being at least one power or ground pad via connected for electrical conduction between each individual power or ground pad and a corresponding individual programmable pad; i) a plurality of power or ground ring vias (28), there being at least one power or ground ring via connected for electrical conduction between each individual power or ground pad and a corresponding individual power or ground ring; j) first and second power or ground planes (42 to 48) located within the package; k) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or ground plane (42); l) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (38) and the second power or ground plane (46); m) a plurality of dedicated power or ground connectors (22) locatd on an exterior surface of the package; and n) a plurality of power or ground connector vias (28), there being at least one power or ground connector via connected for electrical conduction between each individual dedicated power or ground connector (22) and one of the first or second power or ground planes (42 to 48).

Claim 9

A semiconductor chip package, characterized by: a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer (6, 9); d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first and second power or ground rings (34 to 40); g) a plurality of power or ground pads (32) located in a layer (2) within the package, each power or ground pad being configured and located for connection by vias (28) with one selected programmable pad (26) and one of the power or ground rings; h) a plurality of power or ground pad vias (28): there being at least one power or ground pad via connected for electrical conduction between each individual power or ground pad and a corresponding individual programmable pad; i) a plurality of power or ground ring vias (28), there being at least one power or ground ring via connected for electrical conduction between each individual power or ground pad and a corresponding individual power or ground ring; j) first and second power or ground planes (42 to 48) located within the package; k) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or ground plane (42); l) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (38) and the second power or ground plane (46); m) a plurality of dedicated power or ground connectors (22) locatd on an exterior surface of the package; and n) a plurality of power or ground connector vias (28), there being at least one power or ground connector via connected for electrical conduction between each individual dedicated power or ground connector (22) and one of the first or second power or ground planes (42 to 48).

Claim 10

A semiconductor chip package, characterized by: a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of the programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer; d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first and second power or ground rings (34 to 40) located on an exterior surface g) first and second power or ground planes (42 to 48) located within the package; h) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or ground plane (42); i) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (38) and the second power or ground plane (46); j) a plurality of dedicated power or ground connectors (22) located on an exterior surface of the package; and k) a plurality of power or ground connector vias (28), there being at least one power or ground connector via connected for electrical conduction between each individual dedicated power or ground connector and one of the first or second power or ground planes (Fig. 13).

Claim 11

A semiconductor chip package, characterized by: a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of the programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer; d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first and second power or ground rings (34 to 40) located on an exterior surface g) first and second power or ground planes (42 to 48) located within the package; h) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or ground plane (42); i) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (38) and the second power or ground plane (46); j) a plurality of dedicated power or ground connectors (22) located on an exterior surface of the package; and k) a plurality of power or ground connector vias (28), there being at least one power or ground connector via connected for electrical conduction between each individual dedicated power or ground connector and one of the first or second power or ground planes (Fig. 13).

Claim 12

9 A semiconductor chip package, characterized by : a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of the programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer; d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first, second, third, and fourth power or ground rings (34 to 40) located in a layer (3) within the package; g) a plurality of power or ground pads (32) located in a layer (2) within the package, each power or ground pad being configured and located for connection by vias (28) with one selected programmable pad (26) and one of the power or ground rings (34 to 40); h) a plurality of power or ground pad vias (28), there being at least one power or ground pad via connected for electrical conduction between each individual power or ground pad (32) and a corresponding individual programmable pad (26); i) a plurality of power or ground ring vias (28), there being at least one power or ground ring via connected for electrical conduction between each individual power or ground pad (32) and a corresponding individual power or ground ring (34 to 40): j) first, second, third, and fourth power or ground planes (42 to 48) located within the package; k) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or ground plane (42); l) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (36) and the second power or ground plane (44); m) a third power or ground plane via (28) connected for electrical conduction between the third power or ground ring (38) and the third power or ground plane (46); n) a fourth power or ground plane via (28) connected for electrical conduction between the fourth power or ground ring (40) and the fourth power or ground plane (48); o) a plurality of dedicated power or ground connectors (22) located on an exterior surface of the package and; p) a plurality of power or ground connector vias (28) there being at least one power or ground connector via connected for electrical conduction between individual dedicated power or ground connector (22) and one of the first, second, third, or fourth power or ground planes (42 to 48).

Claim 13

9 A semiconductor chip package, characterized by : a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of the programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer; d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first, second, third, and fourth power or ground rings (34 to 40) located in a layer (3) within the package; g) a plurality of power or ground pads (32) located in a layer (2) within the package, each power or ground pad being configured and located for connection by vias (28) with one selected programmable pad (26) and one of the power or ground rings (34 to 40); h) a plurality of power or ground pad vias (28), there being at least one power or ground pad via connected for electrical conduction between each individual power or ground pad (32) and a corresponding individual programmable pad (26); i) a plurality of power or ground ring vias (28), there being at least one power or ground ring via connected for electrical conduction between each individual power or ground pad (32) and a corresponding individual power or ground ring (34 to 40): j) first, second, third, and fourth power or ground planes (42 to 48) located within the package; k) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or ground plane (42); l) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (36) and the second power or ground plane (44); m) a third power or ground plane via (28) connected for electrical conduction between the third power or ground ring (38) and the third power or ground plane (46); n) a fourth power or ground plane via (28) connected for electrical conduction between the fourth power or ground ring (40) and the fourth power or ground plane (48); o) a plurality of dedicated power or ground connectors (22) located on an exterior surface of the package and; p) a plurality of power or ground connector vias (28) there being at least one power or ground connector via connected for electrical conduction between individual dedicated power or ground connector (22) and one of the first, second, third, or fourth power or ground planes (42 to 48).

Claim 14

A semiconductor chip package, characterized by : a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of the programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer (6, 9); d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first, second, third, and fourth power or ground rings (34 to 40) located on an exterior surface (Fig. 13); g) first, second, third, and fourth power or ground planes located (42 to 48) within the package; h) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or round plane (42); i) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (36) and the second power or ground plane (44); j) a third power or ground plane via (28) connected for electrical conduction between the third power or ground ring (38) and the third power or ground plane (46); k) a fourth power or ground plane via (28) connected for electrical conduction between the fourth power or ground ring (40) and the fourth power or ground plane (48); l) a plurality of dedicated power or gound connectors (22) located on an exterior surface of the package and; m) a plurality of power or ground connector vias (28), there being at least one power or ground connector via connected for electrical conduction between each individual dedicated power or ground connector (22) and one of the first, second, third, or fourth power or ground planes (42 - 48).

Claim 15

A semiconductor chip package, characterized by : a) a plurality of programmable pads (26) located on an exterior surface of the package; b) a plurality of signal leads (30) configured on a signal lead layer (6, 9) located within the package; c) a plurality of signal lead vias (28), each signal lead via being connected for electrical conduction between one of the programmable pads (26) and a predetermined signal lead (30) located in the signal lead layer (6, 9); d) a plurality of signal connectors (22) located on an exterior surface of the package; e) a plurality of signal connector vias (28), each signal connector via being connected for electrical conduction between one of the signal leads (30) and a predetermined signal connector (22); f) first, second, third, and fourth power or ground rings (34 to 40) located on an exterior surface (Fig. 13); g) first, second, third, and fourth power or ground planes located (42 to 48) within the package; h) a first power or ground plane via (28) connected for electrical conduction between the first power or ground ring (34) and the first power or round plane (42); i) a second power or ground plane via (28) connected for electrical conduction between the second power or ground ring (36) and the second power or ground plane (44); j) a third power or ground plane via (28) connected for electrical conduction between the third power or ground ring (38) and the third power or ground plane (46); k) a fourth power or ground plane via (28) connected for electrical conduction between the fourth power or ground ring (40) and the fourth power or ground plane (48); l) a plurality of dedicated power or gound connectors (22) located on an exterior surface of the package and; m) a plurality of power or ground connector vias (28), there being at least one power or ground connector via connected for electrical conduction between each individual dedicated power or ground connector (22) and one of the first, second, third, or fourth power or ground planes (42 - 48).