Differential amplifier

Claim 2

A differential amplifier, comprising: input terminals(3,4); output terminals(5,6); load resistor means(7,8) connected to the output terminals(5,6) for generating output voltages; a pair of transistors(Q₁,Q₂), whose emitters are connected with each other, whose collectors are connected to the output terminals(5,6), and whose bases are coupled to the input terminals(3,4); and current source means(1) connected to the emitters of the transistors for providing the emitter currents, characterized by comprising: means(17) for producing negative resistance including level shift circuit means(28,29) for producing additional voltages, the means(17) being connected to the output terminal(3,4).

Claim 3

The amplifier of claim 1, wherein the means(17) for producing negative resistance include: a second pair of transistors(Q₇,Q₈), whose emitters are connected with each other, each of whose collectors is connected to the base of the other transistor of the second pair(Q₇,Q₈) as well as to the output terminals(5,6); second current source means(24,25) connected to the emitters of the second pair of transistors(Q₇,Q₈) for providing the emitter currents to the second pair of transistors(Q₇,Q₈); a terminal resistor(18) connected between the emitters of the transistors of the second pair(Q₇,Q₈); and the level shift circuit means(28,29) for producing additional voltages connected between the base of each transistor of the second pair(Q₇,Q₈) and the output terminals(5,6).

Claim 4

The amplifier of claim 1, wherein the level shift circuit means(28,29) comprises a battery.

Claim 5

The amplifier of claim 1, wherein the level shift circuit means(28,29) comprises at least one diode.

Claim 6

The amplifier of claim 1, wherein the level shift circuit means(28,29) comprises at least one transistor with its base connected to its collector.

Claim 7

The amplifier of claim 1, wherein the level shift circuit means(28,29) comprises a transistor with its base-emitter voltage amplified.

Claim 8

The amplifier of claim 1, wherein the level shift circuit means(28,29) comprises a resistor.

Claim 9

The amplifier of claim 2, further comprising capacitor means(31) connected to the output terminals(5,6) for accumulating charges, and wherein the current source means(1) is a variable current source.

Claim 10

The amplifier of claim 2, wherein the second current source means(24,25) is a variable current source, and wherein the resistance of the terminal resistor(18) is small.

Claim 11

The amplifier of claim 8, further comprising: a second differential amplifier(34), comprising: second input terminals; second output terminals; second load resistor means(7c,8c) connected to the second output terminals for generating output voltage; second means for producing negative resistance connected to the second output terminals and including: a third pair of transistors(Q 1c ,Q 2c ), whose emitters are connected with each other,each of whose collectors is connected to the base of the other transistor of the third pair(Q 1c ,Q 2c ) as well as to the second output terminals; second variable current source means(32) connected to the emitters of the third pair of transistors(Q 1c ,Q 2c ) for providing the emitter currents to the third pair of transistors(Q 1c ,Q 2c ); second level shift means(28c,29c) connected between the base of each transistor of the third pair(Q 1c ,Q 2c ) and the second output terminals for producing additional voltages; second capacitor means(35) connected to the second output terminals for accumulating charges; a fourth pair of transistors(Q 7c ,Q 8c ), whose emitters are connected with each other, whose collectors are connected to the second output terminals, and whose bases are coupled to the second input terminals; constant current source means(1c) connected to the emitters of the fourth pair of transistors(Q 7c ,Q 8c ) for providing the emitter currents, the output terminals being connected to the second input terminals, the input terminals being connected to the second output terminals in reverse direction to the connection between the output terminals and the second input terminals; third output terminals connected to the input terminals; and third input terminals connected to the output terminals.

Claim 12

The amplifier of claim 1, wherein the transistors(Q₁,Q₂) are heterojunction bipolar transistors.

Claim 13

The amplifier of claim 1, wherein the transistors(Q₁,Q₂) are MESFETs(X₁,X₂).

Claim 14

The amplifier of claim 1, wherein the transistors(Q₁,Q₂) are MOSFETs(Y₁,Y₂).

Claim 15

The amplifier of claim 1, wherein the transistors(Q₁,Q₂) are JFETs(Z₁,Z₂).

Claim 16

The amplifier of claim 2, wherein the transistors of the second pair(Q₇,Q₈) are heterojunction bipolar transistors.

Claim 17

The amplifier of claim 2, wherein the transistors of the second pair(Q₇,Q₈) are MESFETs(X₇,X₈).

Claim 18

The amplifier of claim 2, wherein the transistors of the second pair(Q₇,Q₈) are MOSFETs(Y₇,Y₈).

Claim 19

The amplifier of claim 2, wherein the transistors of the second pair(Q₇,Q₈) are JFETs(Z₇,Z₈).

Claim 20

The amplifier of claim 1, further comprising an emitter degeneration resistor(39) between the emitters of the pair of transistors(Q₁,Q₂).