EP0311773A2
Expired / Lapsed
EP
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Non-volatile memory cell
Assignee: International Business Machines Corp
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Filing: 1988-08-18
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Granted: —
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Expires: 2008-08-18
Abstract
Abstract A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes (60, 40, 65). The gate structure (50) includes a gate stack having a dielectric layer (20), a charge storage structure (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means (35, 25). A control electrode (40) is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.
Inventors
- 👤 Roy S. Bass, Jr.
- 👤 Arup Bhattacharyya
- 👤 Gary D. Grise
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/69
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
92 words
A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes, said gate electrode (50) comprising a dielectric structure (20), a charge storage structure (30), a charge injection means (35), and a control electrode (40) for effecting charge transfer to and from said charge storage means (30) through said charge injection means (35, 25), said charge storage means (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride.
Claim 2
Dependent Claim
92 words
A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes, said gate electrode (50) comprising a dielectric structure (20), a charge storage structure (30), a charge injection means (35), and a control electrode (40) for effecting charge transfer to and from said charge storage means (30) through said charge injection means (35, 25), said charge storage means (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride.
Claim 3
Dependent Claim
94 words
A memory cell as recited in claim 1 further comprising: a barrier structure (25) disposed on said first silicon-rich silicon nitride layer (30), a second layer of silicon-rich silicon nitride disposed on said barrier structure, said second silicon-rich silicon nitride layer forming said charge injection means (35) and having an index of refraction of at least 2.35, said second silicon-rich silicon nitride layer having sufficient excess silicon to provide appreciable charge injection enhancement as compared to stoichiometric silicon nitride; and said control electrode (40) being disposed on said second layer of silicon-rich silicon nitride.
Claim 4
Dependent Claim
68 words
The memory cell as recited in claim 2, wherein said first layer (30) of silicon-rich silicon nitride, said barrier structure (25), and said second layer (35) of silicon-rich silicon nitride are formed on only a first portion of said dielectric structure (50), and wherein said control electrode (40) is formed over both said second layer (35) of silicon-rich silicon nitride and remaining portions of said dielectric structure (20).
Claim 5
Dependent Claim
53 words
The memory cell as recited in claims 1, 2 or 3, wherein first and second diffusion regions (60, 65) formed in said substrate (10, 12) abutting said gate electrode structure (50); first means for biasing said first diffusion region; and second means independent of said first means for biasing said second diffusion region.
Claim 6
Dependent Claim
65 words
The memory cell as recited in claim 4, wherein said first means comprises a first metal line that contacts said first diffusion region through a first via formed in a passivation layer coated on the substrate, and wherein said second means comprises a second metal line that contacts said second diffusion region through a second via formed in a passivation layer coated on the substrate.
Claim 7
Dependent Claim
35 words
The memory cell as recited in claims 1 to 5, wherein said dielectric structure (20) is comprised of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
Claim 8
Dependent Claim
23 words
The memory cell as recited in claims 1 to 5, wherein said barrier structure (25) comprises a layer of thermally grown silicon oxide.
Claim 9
Dependent Claim
39 words
The memory cell as recited in claims 1 to 5, wherein said control electrode (40) is comprised of a material selected from the group consisting of doped polysilicon, aluminum, aluminum alloys, refractory metals, refractory metal silicides, and combinations thereof.
Claim 10
Dependent Claim
123 words
An array of memory cells as claimed in claims 1 to 8, comprising: isolation means formed in the substrate for defining discrete portions of the substrate that are isolated from remaining portions of the substrate; a plurality of cells being formed in each of said isolated discrete portions of the substrate, each of said cells comprising an FET having source and drain diffusions formed in the substrate and a gate electrode formed on a portion of the substrate between said source and drain diffusions; first means for biasing said source diffusions; second means for biasing said drain diffusions; and third means for biasing each of said isolated discrete portions of said substrate separately from others of said isolated discrete portions of said substrate.
Claim 11
Dependent Claim
58 words
The array as recited in claim 9, wherein said first means for biasing comprises a first series of conductive lines coupled to a first series of voltage sources, respectively, each one of said first conductive lines being coupled to respective source diffusions of said cells formed in a respective one of said isolated discrete portion of said substrate.
Claim 12
Dependent Claim
58 words
The array as recited in claim 9, wherein said second means for biasing comprises a second series of conductive lines coupled to a second series of voltage sources, respectively, each one of said second conductive lines being coupled to respective drain diffusions of said cells formed in a respective one of said isolated discrete portions of said substrate.
Claim 13
Dependent Claim
30 words
The array as recited in claim 9, wherein said third means for biasing comprises respective substrate bias generators coupled to respective ones of said isolated discrete portions of said substrate.
References Cited (Backward Citations)
No citation records indexed.
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