EP0311111A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Apparatus for assembling data for supply to a scanning output device
Assignee: Advanced Micro Devices Inc
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Filing: 1988-10-07
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Granted: —
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Expires: 2008-10-07
Abstract
Abstract A device controls in real time the assembly of data for a bit map scanning device such as a laser printer under supervisory control of a host processor. The image data words are stored in a source memory and assembled in a video buffer, and automatically scanned out to the scanning device. The host processor generates a simplified set of control words that defines graphics, text and layout of the page to be assembled. An arithmetic logic unit ALU takes care of address calculation for all interfaces. A barrel shifter provides for bit alignment of the image data words in the video memory. Also, background and color combination logic combines the fonts and graphics with background and texture information. A raster interface synchronizes the output of the assembled data with the scanning device. Three basic modes are supported: 1) dispatch mode, 2) font read/write mode, and 3) graphics load mode. The dispatch mode is the normal operational mode which provides for dispatching data from a source memory location to the video memory for supplying data from the video memory out to the raster printer. The font read/write mode, gives the host the ability to read/write font or graphics data from/to the source memory or the video memory. The graphics load mode provides for transfer of a bit-mapped window of data to the video memory. The video memory can be divided into two video bands. While one of the video bands is being read for supply of output data to the scanning device, data in the second band is being filled with font and graphics information using dispatch. After scanning all data out of the first band, the apparatus switches to the second band for printing and refills the first band with new data using dispatch.
Inventors
- 👤 Shinkyo Kaku
- 👤 Chung-Li Yu
- 👤 Greg W. Barr
- 👤 Steven Gary
- 👤 David R. Staab
- 👤 George W. Li
- 👤 Anan Nagarajan
- 👤 Shabbir M. Latif
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 19:35
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/12; G06F3/1297; G06K; G06K15/00; G06F3/1293; G06K15/02; G06K15/12; G06K15/1276; G06K15/128; G06K2215/00; G06K2215/0002; G06K2215/0062; G06K2215/0065; G06K2215/0077; G06K2215/008; G06K2215/0082; G06K2215/0094
Claims Analysis
Total Claims: 47
Claim 1
Independent Claim
237 words
An apparatus for assembling image data word for supply to a two-dimensional scanning device under control of a processor that generates control words, image data words being stored in an source memory accessible in response to source addresses and image data words being assembled in an assembly memory accessible in response to assembly addresses, comprising: a control interface means (14,54), adapted for communication with the processor, for receiving the control words; storage means (65), in communication with the control interface means, for storing and outputting the control words; control means (55), in communication with the control interface means and a storage means, for generating transaction control signals in response to the control words; address generating means (68, 70), in communication with the storage means and the control means, for generating the source addresses and the assembly addresses in response to the transaction control signals and the control words; image data interface means (15, 16, 58, 62), adapted for communication with the source memory and the assembly memory and coupled to the control means and address generating means, for reading and writing image data words in the source memory and the assembly memory in response to transaction control signals, source addresses and assembly addresses; and scanner interface means (13,61), adapted for communication with the scanning device and coupled to the assembly interface means, for supplying assembled data words read by the assembly interface means to the scanning device.
Claim 2
Independent Claim
237 words
An apparatus for assembling image data word for supply to a two-dimensional scanning device under control of a processor that generates control words, image data words being stored in an source memory accessible in response to source addresses and image data words being assembled in an assembly memory accessible in response to assembly addresses, comprising: a control interface means (14,54), adapted for communication with the processor, for receiving the control words; storage means (65), in communication with the control interface means, for storing and outputting the control words; control means (55), in communication with the control interface means and a storage means, for generating transaction control signals in response to the control words; address generating means (68, 70), in communication with the storage means and the control means, for generating the source addresses and the assembly addresses in response to the transaction control signals and the control words; image data interface means (15, 16, 58, 62), adapted for communication with the source memory and the assembly memory and coupled to the control means and address generating means, for reading and writing image data words in the source memory and the assembly memory in response to transaction control signals, source addresses and assembly addresses; and scanner interface means (13,61), adapted for communication with the scanning device and coupled to the assembly interface means, for supplying assembled data words read by the assembly interface means to the scanning device.
Claim 3
Dependent Claim
107 words
The apparatus of claim 1, wherein the image data interface means includes: source interface means (15,62), adapted for communication with the source memory and coupled to the control means and the address generating means, for reading and writing image data words in the source memory in response to transaction control signals and source addresses; assembly interface means (16,58), adapted for communication with the assembly memory and coupled to the control means, the address generating means and the source interface means, for assembling image data words in the assembly memory and for reading assembled data in the assembly memory in response to transaction control signals and assembly addresses.
Claim 4
Dependent Claim
184 words
The apparatus of claim 2, wherein the control means includes: mode control means (74, Figs. 13, 14, 15), connected to the storage means and responsive to a control word stored in the storage means that indicates a selected mode of operation for the apparatus, for generating transaction type signals to implement the selected mode; scan control means (72, Fig. 12), connected to the storage means and the scanner interface means and responsive to communication with the scanner interface means and control words stored in the storage means, for generating transaction type signals to maintain the supply of assembled data words to the scanning device; transaction type selecting means (1725), connected to the mode control means and the scan control means, for selecting a transaction type signal from the scan control means of the mode control means; and transaction control means (75, Figs. 16, 17, 18, 19, 20), connected to the transaction type selecting means, the address generating means, the assembly interface means, the source interface means and the storage means and responsive to the selected transaction type signal, for generating the transaction control signals.
Claim 5
Dependent Claim
105 words
The apparatus of claim 3, wherein the assembly memory includes a buffer address space including a first band and a second band, and the control means further includes: band control means (73, Fig. 11), connected to the scan control means, the mode control means and the transaction control means, for coordinating access to the first band and the second band so that one band may be accessed by the assembly interface means for supply of data to the scanner interface means and the other band may be accessed in a multiplexed manner by the assembly interface means for writing data from the source interface means.
Claim 6
Dependent Claim
83 words
The apparatus of claim 1, wherein the control words include a control command word (CCW, Fig. 5), a source command word (SCW, Figs. 6 and 7) and a destination command word (DCW, Fig. 9) and wherein: the control means is responsive to the control command word in generating transaction control signals (1601-1606, 1612-1630, 1638, 1639); and the address generating means is responsive to the source command word in generating source addresses, and is responsive to the destination command word in generating assembly addresses.
Claim 7
Dependent Claim
165 words
The apparatus of claim 2, wherein the control words include a control command word (CCW, Fig. 5), indicating one of a plurality of modes of operation, one of the plurality of modes of operation being a dispatch mode, and the control words include a source command word (SCW, Figs. 6 and 7) including a source address of a source image block and a destination command word (DCW, Fig. 9), including a destination address of a memory storage location, a source image block including one or more image data words and a memory storage location including data locations addressable by one or more assembly addresses, and wherein: the control means is responsive to the control command word to generate transaction control signals in the dispatch mode so that the source interface means reads the image data word in the source address and transfers the image data word to the assembly interface means, and the assembly interface means stores the image data word at the assembly address.
Claim 8
Dependent Claim
92 words
The apparatus of claim 6, wherein the assembly memory includes a buffer address space including a first band and a second band, and the control means further includes: band control means (73, Fig. 11), in communication with the assembly interface means, for coordinating access to the first band and the second band so that one band may be accessed by the assembly interface means for supply of data to the scanner interface means and the other band is accessed by the assembly interface means for writing data from the source interface means.
Claim 9
Dependent Claim
131 words
The apparatus of claim 7, wherein the memory storage location identified by the destination address in the destination command word is addressable by a number of assembly addresses that correspond to the size of the source image block, and wherein the first one of said plurality of assembly addresses resides in one of the first and second bands and the remaining ones of the plurality of assembly addresses reside in the other of the first and second bands, and wherein the control means further includes: means, in communication with the control interface means and the address generating means, for generating an interrupt (INTR, DI) when an assembly address is generated by the address generating means that resides outside the one band in which the first assembly address of the plurality resided.
Claim 10
Dependent Claim
38 words
The apparatus of claim 8, wherein the control means further includes: means for writing parameters (DI) indicating the nature of the interrupt to the storage means, whereby the processor may access the parameters through the control interface means.
Claim 11
Dependent Claim
47 words
The apparatus of claim 6, wherein the source command word further includes data indicating the size of the source image block (SIHR, SIWR), and the address generating means generates a plurality of source addresses in response to the source address of the image block and its size.
Claim 12
Dependent Claim
48 words
The apparatus of claim 6, wherein the source command word further includes data indicating the size of the source image block (SIHR, SIWR), and the address generating means generates a plurality of assembly addresses in response to the destination virtual address of the image block and its size.
Claim 13
Dependent Claim
173 words
The apparatus of claim 2, wherein the control words include a control command word indicating one of a plurality of modes of operation, one of the plurality of modes of operation being a dispatch mode and the control words include a source command word including a source address (SCAR) of a source image block and a destination command word including a destination virtual address (DCAR) of a memory storage location, a source image block including one or more image data words and a memory storage location including data locations addressable by one or more assembly addresses, and wherein: the control means is responsive to the control command word to generate transaction control signals in the dispatch mode so that the address generating means translates the destination virtual address to a real assembly address, the source interface means reads the image data word in the real source address and transfers the image data word to the assembly interface means, and the assembly interface means stores the image data word in the real assembly address.
Claim 14
Dependent Claim
47 words
The apparatus of claim 12, wherein the source command word further includes data indicating the size of the source image block (SIHR, SIWR), and the address generating means generates a plurality of source addresses in response to the source address of the image block and its size.
Claim 15
Dependent Claim
48 words
The apparatus of claim 12, wherein the source command word further includes data indicating the size of the source image block (SIHR, SIWR), and the address generating means generates a plurality of assembly addresses in response to the destination address and the size of the source image block.
Claim 16
Dependent Claim
94 words
The apparatus of claim 12, wherein the assembly memory includes a buffer address space (VBBR 21) including a first band and a second band and the control means further includes: band control means (73, Fig. 11), in communication with the assembly interface means, for coordinating access to the first band and the second band so that one band may be accessed by the assembly interface means for supply of data to the scanner interface means and the other band is accessed by the assembly interface means for writing data from the source interface means.
Claim 17
Dependent Claim
131 words
The apparatus of claim 15, wherein the memory storage location identified by the destination address in the destination command word is addressable by a number of assembly addresses that correspond to the size of the source image block, and wherein the first one of said plurality of assembly addresses resides in one of the first and second bands and the remaining ones of the plurality of assmebly addresses reside in the other of the first and second bands, and wherein the control means further includes: means, in communication with the control interface means and the address generating means, for generating an interrupt (INTR, DI) when an assembly address is generated by the address generating means that resides outside the one band in which the first assembly address of the plurality resided.
Claim 18
Dependent Claim
38 words
The apparatus of claim 16, wherein the control means further includes: means for writing parameters (DI) indicating the nature of the interrupt to the storage means, whereby the processor may access the parameters through the control interface means.
Claim 19
Dependent Claim
135 words
The apparatus of claim 2, wherein the control words include a control command word indicating one of a plurality of modes of operation, one of the plurality of modes of operation is a font load mode, and the control words include a destination command word including a destination address (DCAR) of a memory storage location, a memory storage location including data locations addressable by one of more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the font load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the source interface means, and the source interface means writes the image data word to the source address indicated by the destination address.
Claim 20
Dependent Claim
37 words
The apparatus of claim 18, wherein the address generating means generates a plurality of source addresses, one in response to each image data word of the image block written to the control interface means by the processor.
Claim 21
Dependent Claim
140 words
The apparatus of claim 2, wherein the control words include a control command word (CCW, Fig. 5) indicating one of a plurality of modes of operation, one of the plurality of modes of operation being a source load mode; and the control words include a destination command word (DCW, Fig. 9) including a destination address of a memory storage location in the source load mode, a memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the source load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the source interface means, and the source interface means writes the image data word to the source address.
Claim 22
Dependent Claim
36 words
The apparatus of claim 20, wherein the address generating means generates a plurality of source addresses, one in response to each image data word of the image block written tothe control interface means by the processor.
Claim 23
Dependent Claim
142 words
The apparatus of claim 2, wherein the control words include a control command word (CCW, Fig. 5) indicating one of a plurality of modes of operation, one of the plurality of modes of operation being a graphics load mode; and the control words include a destination command word (DCW, Fig. 9) including a destination address of a memory storage location for a graphics image block in the graphics load mode, a memory storage location including data locations addressable by assembly addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the graphics load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the assembly interface means, and the assembly interface means writes the image data word to the assembly address.
Claim 24
Dependent Claim
69 words
The apparatus of claim 22, wherein the source command word (SCW, Figs. 6 and 7) in the graphics load mode that includes data indicating the number of image data words per line (SIWR) in the graphics image block, and the address generating means generates a plurality of assembly addresses in response to the destination address and the number of image data words per line in the graphics image block.
Claim 25
Dependent Claim
117 words
The apparatus of claim 2, wherein the control words include a control command word (CCW, Fig. 5) indicating one of a plurality or modes of operation, one of the plurality of modes of operation being a source read mode; and the control words include a destination command word (DCW, Fig. 9) including a source address of a memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the source read mode so that the source interface means reads a data word from the memory storage location and transfers the data word to the control interface means.
Claim 26
Dependent Claim
30 words
The apparatus of claim 24, wherein the address generating means generates a plurality of source addresses, one in response to each read by the processor to the control interface means.
Claim 27
Dependent Claim
253 words
The apparatus of claim 6, wherein the control words include a control command word (CCW, Fig, 5) indicating one of a plurality of modes of operation, one of the plurality of modes of operation being a dispatch mode, and the control words include a source command word (SCW0, Fig. 6) including a source address of a source image block, a texture command word (SCW1, Fig. 7) including a source address of a texture image block, and a destination command word including a destination address of a memory storage location, a source image block including one or more image data words, a texture image block including one or more texture data words, and a memory storage location including data locations addressable by one or more assembly addresses, the apparatus further including: combining means (71, Figs. 30-31), in communication with the control means, the source interface means and the assembly interface means, for combining image data words and texture data words to generate textured data words; and wherein the control means is responsive to the control command word to generate transaction control signals in the dispatch mode so that the source interface means reads the image data word and the texture data word in the respective source addresses and transfers the image data word and texture data word to the combining means, the combining means combines the image data word and the texture data word to generate a textured data word, and the assembly interface means stores the textured data word in the assembly address.
Claim 28
Dependent Claim
231 words
The apparatus of claim 2, wherein the control words include a control command word (CCW, Fig. 5) indicating one of a plurality of modes of operation, one of the plurality of modes of operation being a dispatch mode, and the control word include a source command word (SCW, Figs. 6-7) including a source address (SCAR) of a source image block, and a destination command word, (Fig. 9) including a destination address (DCAR(28:4)) of a memory storage location and an offset (DCAR(3:0)) defining a bit alignment within the storage location, a source image block including one or more image data words and a memory storage location including data locations addressable by one or more assembly addresses, the apparatus further including: aligning means (71, Figs. 30-31), in communication with the storage means, the control means, the assembly interface means, and the source interface means, for aligning image data words on bit boundaries in response to the offset; and wherein the control means is responsive to the control command word to generate transaction control signals in the dispatch mode so that the source interface means reads the image data word in the source address and transfers the image data word to the aligning means, the aligning means aligns the image data word to generate an aligned image data word, and the assembly interface means stores the aligned image data word in the assembly address.
Claim 29
Independent Claim
339 words
An apparatus formed on an integrated circuit for assembling image data words for supply to a raster printer under control of a processor that generates control words, image data words being stored in a source memory accessible in response to source addresses and image data words being assembled in an assembly memory accessible in response to assembly addresses, the control words including a code indicating one of a plurality of modes of operation (M0-M3), a code identifying a source address of an image block including one or more image data words (SCAR) and a code indicating a destination address of a memory storage location in the assembly memory (DCAR) at which the source image block is to be stored, comprising: a control interface means (14, 54), adapted for communication with the processor, for receiving the control words; storage means (65), in communication with the control interface means, for storing and outputting the control words; control means (55), in communication with the control interface means and the storage means, for generating transaction control signals in response to the control words; address generating means (68, 70), in communication with the storage means and the control means, for generating the source addresses and the assembly addresses in response to the transaction control signals and the codes indicating the source address of the image data block and the destination address of the memory storage location in the assembly memory in which the image block is to be stored; image data interface means (15, 16, 58, 62), adapted for communication with the source memory and assembly memory and coupled to the control means and the address generating means, for reading and writing image data words in the source memory and the assembly memory in response to the transaction control signals and the source addresses and assembly addresses; and printer interface means (13, 61), adapted for communication with the printer and coupled to the image data interface means, for supplying data words from the assembly memory through the image data interface means to the printer.
Claim 30
Independent Claim
339 words
An apparatus formed on an integrated circuit for assembling image data words for supply to a raster printer under control of a processor that generates control words, image data words being stored in a source memory accessible in response to source addresses and image data words being assembled in an assembly memory accessible in response to assembly addresses, the control words including a code indicating one of a plurality of modes of operation (M0-M3), a code identifying a source address of an image block including one or more image data words (SCAR) and a code indicating a destination address of a memory storage location in the assembly memory (DCAR) at which the source image block is to be stored, comprising: a control interface means (14, 54), adapted for communication with the processor, for receiving the control words; storage means (65), in communication with the control interface means, for storing and outputting the control words; control means (55), in communication with the control interface means and the storage means, for generating transaction control signals in response to the control words; address generating means (68, 70), in communication with the storage means and the control means, for generating the source addresses and the assembly addresses in response to the transaction control signals and the codes indicating the source address of the image data block and the destination address of the memory storage location in the assembly memory in which the image block is to be stored; image data interface means (15, 16, 58, 62), adapted for communication with the source memory and assembly memory and coupled to the control means and the address generating means, for reading and writing image data words in the source memory and the assembly memory in response to the transaction control signals and the source addresses and assembly addresses; and printer interface means (13, 61), adapted for communication with the printer and coupled to the image data interface means, for supplying data words from the assembly memory through the image data interface means to the printer.
Claim 31
Dependent Claim
133 words
The apparatus of claim 28, wherein the image data interface means includes: a source interface means (15, 62), adapted for communication with the source memory and coupled to the control means and the address generating means, for reading and writing image data words in the source image block in response to the transaction control signals and source addresses supplied by the address generating means; and assembly interface means (16, 58), adapted for communication with the assembly memory and coupled to the control means, the address generating means and the source interface means, for assembling image data words in the assembly memory in response to the assembly addresses supplied by the address generating means, and for reading assembled data in the assembly memory in response to transaction control signals for supply to the printer.
Claim 32
Dependent Claim
84 words
The apparatus of claim 28, wherein one of the plurality of modes is the dispatch mode, and wherein: the control means is responsive to the control words to generate transaction control signals in the dispatch mode so that the image data interface means reads the image data block from the source memory in response to addresses supplied by the address generating means, and transfers the image data block to the assembly memory in response to the assembly addresses supplied by the address generating means.
Claim 33
Dependent Claim
96 words
The apparatus of claim 30, wherein the assembly memory includes a buffer address space (VBB, 28) including a first band and a second band, and the control means further includes: band control means (73, Fig. 11), in communication with the image data interface means, for coordinating access to the first band and the second band so that one band (SBAND) may be accessed by the image data interface means for supply of data to the printer and the other band (DBAND) is accessed by the image data interface means for writing data from the source memory.
Claim 34
Dependent Claim
126 words
The apparatus of claim 31, wherein the memory storage location identified by the destination address is addressable by a number of assembly addresses that correspond to the size of the source image block, and wherein the first one of said plurality of assembly addresses may reside in one of the first and second bands while another one of the plurality of assembly addresses reside in the other of the first and second bands, and wherein the control means further includes: means, in communication with the control interface means and the address generating means, for generating an interrupt (DI, INTR) when an assembly address is generated by the address generating means that resides outside the one band in which the first assembly address of the plurality resides.
Claim 35
Dependent Claim
38 words
The apparatus of claim 32, wherein the control means further includes: means for writing parameters (DI) indicating the nature of the interrupt to the storage means, whereby the processor may access the parameters through the control interface means.
Claim 36
Dependent Claim
158 words
The apparatus of claim 28, wherein the control words further include a code indicating a source address of a texture image block including one or more data words, and further including: combining means (71, Figs. 30-31), in communication with the control means and the image data interface means, for combining image data words and texture data words to generate textured data words, and wherein the control means is responsive to the control words in the dispatch mode to generate transaction control signals so that the image data interface means reads the image data word and the texture data word in the respective source addresses and transfers the image data word and texture data word to the combining means, the combining means combines the image data word and the texture data word to generate a textured data word, and the image data interface means stores the textured data word in the assembly address supplied by the address generating means.
Claim 37
Dependent Claim
157 words
The apparatus of claim 28, wherein the code indicating the destination address of a memory storage location in the assembly memory includes an offset value defining bit alignment within the storage location, the apparatus further including: aligning means (71, Figs. 30-31), in communication with the storage means, the control means and the image data interface means, for aligning image data words on bit boundaries in response to the offset, and wherein the control means is responsive to the control words in the dispatch mode to generate transaction control signals so that the image data interface reads the image data word and the source address supplied by the address generating means and transfers the image data word to the aligning means, the aligning means aligns the image data word to generate an aligned image data word, and the image data interface means stores the aligned image data words in the assembly address supplied by the address generating means.
Claim 38
Dependent Claim
47 words
The apparatus of claim 30, wherein the source command word further includes data indicating the size of the source image block (SIHR, SIWR), and the address generating means generates a plurality of source addresses in response to the source address of the image block and its size.
Claim 39
Dependent Claim
48 words
The apparatus of claim 30, wherein the source command word further includes data indicating the size of the source image block (SIHR, SIWR), and the address generating means generates a plurality of assembly addresses in response to the destination address and the size of the source image block.
Claim 40
Dependent Claim
113 words
The apparatus of claim 28, wherein one of the plurality of modes of operation is a font load mode, and the control words include a code identifying a destination address (DCAR) of a memory storage location, a memory storage location including data locations addressable by one of more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the font load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the destination address.
Claim 41
Dependent Claim
37 words
The apparatus of claim 38, wherein the address generating means generates a plurality of source addresses, one in response to each image data word of an image block written to the control interface means by the processor.
Claim 42
Dependent Claim
116 words
The apparatus of claim 28, wherein one of the plurality of modes of operation is a source load mode; and the control words include a code indicating destination address of a memory storage location in the source load mode, a memory storage location including data locations addressable by one or more source addresses, and wherein: the control means is responsive to the control command word to generate transaction control signals in the source load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the destination address.
Claim 43
Dependent Claim
37 words
The apparatus of claim 40, wherein the address generating means generates a plurality of destination addresses, one in response to each image data word of an image block written by the processor to the control interface means.
Claim 44
Dependent Claim
121 words
The apparatus of claim 28, wherein one of the plurality of modes of operation is a graphics load mode and the control words include a code indicating a destination address of a memory storage location for a graphics image block in the graphics load mode, a memory storage location including data locations addressable by assembly or source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the graphics load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the destination address.
Claim 45
Dependent Claim
67 words
The apparatus of claim 42, wherein the control words (SCW, Figs. 6 and 7) in the graphics load mode include data indicating the number of image data words per line (SIWR) in the graphics image block, and the address generating means generates a plurality of assembly addresses in response to the destination address and the number of image data words per line in the graphics image block.
Claim 46
Dependent Claim
94 words
The apparatus of claim 28, wherein one of the plurality of modes of operation is a source read mode; and the control words include a code indicating a source address (DCAR) of a memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the source read mode so that the image data interface means reads a data word from the memory storage location and transfers the data word to the control interface means.
Claim 47
Dependent Claim
30 words
The apparatus of claim 44, wherein the address generating means generates a plurality of source addresses, one in response to each read by the processor to the control interface means.
References Cited (Backward Citations)
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