EP0310446A2
Expired / Lapsed
EP
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Cache memory management method
Assignee: COMPUTER CONSOLES Inc (a Delaware corporation)
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Filing: 1988-09-30
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Granted: —
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Expires: 2008-09-30
Abstract
Abstract A data processing system includes an instruction processor (101) and a main memory (105) that has such a relatively large number of addressable memory locations that the main memory has a latency time that is substantially longer than the time in which the instruction processor can initiate successive accesses to the memory. Buffer memory means is provided having a relatively small number of buffer locations into which data read from the main memory are stored initially as a duplicate of data stored in the main memory and thereafter modified and marked dirty. Sequentially operating means (109) including multi-biffer means provides for replacing data marked dirty with other data read from the main memory and thereafter causing the data marked dirty to be written into the main memory.
Inventors
- 👤 Jack Benkual
- 👤 Shmuel Shottan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 02:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/28; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
128 words
In a data processing system that includes an instruction processor (101) and a main memory (105) with such a relatively large number of addressable memory locations that the main memory has a latency time that is substantially longer than the time in which the instruction processor can initiate successive accesses to the main memory, a subsystem characterised by: buffer memory means (201) having a relatively small number of buffer locations into which data read from the main memory are stored initially as a duplicate of data stored in the main memory and thereafter modified and marked dirty; sequentially operating means (109) for replacing data marked dirty with other data read from the main memory and thereafter causing the data marked dirty to be written into the main memory.
Claim 2
Dependent Claim
128 words
In a data processing system that includes an instruction processor (101) and a main memory (105) with such a relatively large number of addressable memory locations that the main memory has a latency time that is substantially longer than the time in which the instruction processor can initiate successive accesses to the main memory, a subsystem characterised by: buffer memory means (201) having a relatively small number of buffer locations into which data read from the main memory are stored initially as a duplicate of data stored in the main memory and thereafter modified and marked dirty; sequentially operating means (109) for replacing data marked dirty with other data read from the main memory and thereafter causing the data marked dirty to be written into the main memory.
Claim 3
Dependent Claim
62 words
A subsystem according to claim 1, wherein the buffer memory means comprises a processor-to-memory buffer (301) and a memory-to-processor buffer (303), and wherein the data marked dirty are stored into the procesor-to-memory buffer during the latency time to read the replacement data, and wherein the replacement data are stored into the memory-to-processor buffer before the data marked dirty are written to memory.
Claim 4
Dependent Claim
42 words
A subsystem according to claim 2, wherein each buffer has multiple registers (301-0 to 301-7 and 303-0 to 303-7) for use in support of means (BS0 to BS5) for susbtantially matching the bandwidth of memory-to-buffer transfers with the bandwidth of buffer-to-processor transfers.
Claim 5
Dependent Claim
30 words
A subsystem according to any one of claims 1 to 3, wherein the buffer memory means is defined by a set of integrated circuit chips organized for bit slice arangement.
Claim 6
Dependent Claim
25 words
A subsystem according to claim 4, wherein each such chip includes plurality of memory cells that the chip contributes to define the buffer memory means.
Claim 7
Independent Claim
146 words
A method of operating a data processing system in which a cache memory is provided to store data in cache locations each of which is associated with a large number of main memory locations having a latency time, the method comprising: writing data into a cache location and in the course of doing so setting a dirty bit for that cache memory location; initiating a read-replacement sequence of steps upon detecting a cache miss on that cache location; proceeding with the read-replacement operation by initiating a read of data from an addressed main memory location; further proceeding during the latency time to transfer data from that cache location to a processor-to-memory buffer; transferring data read from the addressed memory location, through a memory-to-processor buffer, to that cache location; and performing a write to another addressed memory location to store in it data from the processor-to-memory buffer.
Claim 8
Independent Claim
146 words
A method of operating a data processing system in which a cache memory is provided to store data in cache locations each of which is associated with a large number of main memory locations having a latency time, the method comprising: writing data into a cache location and in the course of doing so setting a dirty bit for that cache memory location; initiating a read-replacement sequence of steps upon detecting a cache miss on that cache location; proceeding with the read-replacement operation by initiating a read of data from an addressed main memory location; further proceeding during the latency time to transfer data from that cache location to a processor-to-memory buffer; transferring data read from the addressed memory location, through a memory-to-processor buffer, to that cache location; and performing a write to another addressed memory location to store in it data from the processor-to-memory buffer.
References Cited (Backward Citations)
No citation records indexed.
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