Page printing system using a virtual memory

Claim 2

A printer processing system in which page layout information is processed to form a page image data compris­ing, an image processor receiving the page layout informa­tion and providing the page image data at logical addresses, a physical memory for storing page image data at physical addresses, management means including map means for maintaining a correspondence between physical addresses and logical addresses, control means for sequencing said system, said control means including means for sequentially providing logical addresses to said map means to provide corresponding physi­cal addresses, means for accessing said page image data from said physical memory using real addresses translated from logical addresses which have been allocated to said physical memory.

Claim 3

The processing system of Claim 1, wherein said page layout information includes one or more first data values having different logical addresses representing pixels of all one type within an area and includes one or more second data values, each having different logical addresses to represent different pixels of variable type within an area, said allocation means operating to allocate the logical addresses of said first data values to the same first physical address and to allocate each of the logical ad­dresses for said second data values to different second physical addresses.

Claim 4

The processing system of Claim 2, wherein said physical memory is a random access memory for storing data in said second physical addresses.

Claim 5

The processing system of Claim 3, wherein said first physical addresses are stored in said map unit whereby accesses to said random accesses memory are not required for said first data values.

Claim 6

The processing system of Claim 1, wherein said manage­ment means includes means for allocating physical addresses in said physical memory which correspond to logical address­es for page image data during a painting process and in­cludes means for deallocating physical addresses in said physical memory in response to a shipout process.

Claim 7

The processing system of Claim 1, including permuter means for permuting the logical addresses from said proces­sor whereby non-contiguous logical addresses are transformed to contiguous logical addresses associated with a patch.

Claim 8

The processing system of Claim 6, wherein said map unit includes means for translating the logical addresses associ­ated with a patch to contiguous physical addresses in said physical memory.

Claim 9

The processing system of Claim 6, wherein said patch addresses correspond to small rectangular regions on a page to be printed.

Claim 10

The processing system of Claim 1, wherein said logical addresses are a power of 2 whereby said page image data is defined by logical addresses having a power of 2.

Claim 11

The processing system of Claim 1, wherein said logical addresses have an address field for specifying logical addresses for page image data in a logical image plane and for specifying other system data in a logical system memory as part of the same logical memory address space.

Claim 12

A page printing system in which page information is processed to form a printed page comprising, a printer operating at a printing rate to print the printed page, during a printing time, as an array of vari­able intensity pixels in response to stored page image data, an image processor for processing the page layout information to form said page image data at logical address­es, a physical memory for storing page image data at real addresses, a logical to real translator for translating the logical addresses to real addresses, an allocator for maintaining a correspondence between physical addresses and logical addresses in said physical memory, control means for sequencing said system, said control means including means for sequentially accessing logical addresses, means for accessing image data from said physical memory for real addresses translated from logical addresses which have been allocated to said physical memory, means for printing said page image data at the logical address locations to control the printing of pixels to form the printed page, said printing of pixels is controlled by the data accessed from said physical memory at logical addresses corresponding to physical addresses in said memory.

Claim 13

A page printing system in which page information is processed to form a printed page comprising, a printer operating at a printing rate to print the printed page, during a printing time, as an array of vari­able intensity pixels in response to stored page image data, an image processor for processing the page layout information to form said page image data at logical address­es, a physical memory for storing page image data at real addresses, a logical to real translator for translating the logical addresses to real addresses, an allocator for maintaining a correspondence between physical addresses and logical addresses in said physical memory, control means for sequencing said system, said control means including means for sequentially accessing logical addresses, means for accessing image data from said physical memory for real addresses translated from logical addresses which have been allocated to said physical memory, means for printing said page image data at the logical address locations to control the printing of pixels to form the printed page, said printing of pixels is controlled by the data accessed from said physical memory at logical addresses corresponding to physical addresses in said memory.