EP0310111A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory incorporating logic LSI and method for testing the same LSI
Assignee: Hitachi Ltd
•
Filing: 1988-09-30
•
Granted: —
•
Expires: 2008-09-30
Abstract
Abstract This invention relates to a memory incorporating logic LSI and a method for testing the same LSI. Signal path switching circuit portions (50, 51) are disposed in the course of a memory portion (30) and a logic circuit portion (20) so that a test signal input and an output signal can be observed at the input and output terminal portion (40) so as to be able to effect a dynamic function test of the memory portion (30). Further there is disposed a logic circuit testing signal memory circuit portion (80), which switches over the signal path switching circuit portions (50, 51) to the logic circuit portion (20) so as to be able to effect a test of the logic circuit portion (20), independently of the state of the memory portion (30)
Inventors
- 👤 Kazumi Hatayama
- 👤 Terumine Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G06; G06F; G06F11/00; G06F11/22; G06F11/2273
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
263 words
A memory incorporating logic LSI comprising: an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is transmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a memory test input signal path (111), with which said input and output terminal portion (40) is connected and through which a signal for memory test is inputted and transmitted; a memory test output signal path (109), which outputs the output signal from said memory portion (30) to said input and output terminal portion (40); and a signal path switching circuit portion (50) disposed in the course of said first signal path (108, 109, 111), which transmits the signal from said memory test input signal path (111) by switching off said first signal path (108) from said logic circuit portion (20) on the basis of said operation mode signal.
Claim 2
Dependent Claim
263 words
A memory incorporating logic LSI comprising: an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is transmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a memory test input signal path (111), with which said input and output terminal portion (40) is connected and through which a signal for memory test is inputted and transmitted; a memory test output signal path (109), which outputs the output signal from said memory portion (30) to said input and output terminal portion (40); and a signal path switching circuit portion (50) disposed in the course of said first signal path (108, 109, 111), which transmits the signal from said memory test input signal path (111) by switching off said first signal path (108) from said logic circuit portion (20) on the basis of said operation mode signal.
Claim 3
Dependent Claim
56 words
A memory incorporating logic LSI according to Claim 1, wherein an input terminal, which applies a test signal from the exterior to said memory test input signal path (111), is used in common as an input terminal, through which a signal is inputted from the exterior to said logic circuit portion (20) at the usual operation.
Claim 4
Dependent Claim
55 words
A memory incorporating logic LSI according to Claim 1, wherein an output terminal, which outputs a signal from said memory test input signal path (111) to the exterior, is used in common as an input terminal, through which a signal is inputted from the exterior to said logic circuit portion (20) at the usual operation.
Claim 5
Dependent Claim
56 words
A memory incorporating logic LSI according to Claim 1, wherein an input terminal, which applies a test signal from the exterior to said memory test input signal path (111), is used in common as an output terminal, through which a signal is outputted from said logic circuit portion (20) to the exterior at the usual operation.
Claim 6
Dependent Claim
55 words
A memory inocrporating logic LSI according to Claim 1, wherein an output terminal, which outputs a signal from said memory test input signal path (111) to the exterior, is used in common as an output terminal, through which a signal is outputted from said logic circuit portion (20) to the exterior at the usual operation.
Claim 7
Dependent Claim
270 words
A memory incorporating logic LSI comprising: an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is transmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a logic circuit testing signal memory circuit portion (80) having an output portion outputting a predetermined logic circuit test pattern inputted from said input and output terminal portion (40), which inputs a signal outputted from said logic circuit portion (20) to said first signal path (108) and outputs it to said input and output terminal portion (40); and a signal path switching circuit portion (51) disposed in the course of said second signal path (106, 107, 110), which transmits the signal from said output portion of said logic circuit testing signal memory circuit portion (80) by switching off said second signal path (106) from said memory portion (30) on the basis of said operation mode signal.
Claim 8
Dependent Claim
270 words
A memory incorporating logic LSI comprising: an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is transmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a logic circuit testing signal memory circuit portion (80) having an output portion outputting a predetermined logic circuit test pattern inputted from said input and output terminal portion (40), which inputs a signal outputted from said logic circuit portion (20) to said first signal path (108) and outputs it to said input and output terminal portion (40); and a signal path switching circuit portion (51) disposed in the course of said second signal path (106, 107, 110), which transmits the signal from said output portion of said logic circuit testing signal memory circuit portion (80) by switching off said second signal path (106) from said memory portion (30) on the basis of said operation mode signal.
Claim 9
Dependent Claim
373 words
a memory incorporating logic LSI comprising: an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is transmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a memory test input signal path (111), with which said input and output terminal portion (40) is connected and through which a signal for memory test is inputted and transmitted; a memory test output signal path (109), which outputs the output signal from said memory portion (30) to said input and output terminal portion (40); a logic circuit testing signal memory circuit portion (80) having an output portion outputting a predetermined logic circuit test pattern inputted from said input and output terminal portion (40), which inputs a signal outputted from said logic circuit portion (20) to said first signal path (108) and outputs it to said input and output terminal portion (40); and signal path switching circuit portions (50 and 51) disposed in the course of said first and said second signal paths (106, 107, 111; 106, 107, 110), respectively, which transmits the signal from said memory test input signal path (111) by switching off said first signal path (108) from said logic circuit portion (20), when said operation mode signal is at the memory test mode, and the signal from said output portion of said logic circuit testing signal memory circuit portion (80) by switching off said second signal path (106) from said memory portion (30), when said operation mode signal is at the logic circuit test mode.
Claim 10
Dependent Claim
373 words
a memory incorporating logic LSI comprising: an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is transmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a memory test input signal path (111), with which said input and output terminal portion (40) is connected and through which a signal for memory test is inputted and transmitted; a memory test output signal path (109), which outputs the output signal from said memory portion (30) to said input and output terminal portion (40); a logic circuit testing signal memory circuit portion (80) having an output portion outputting a predetermined logic circuit test pattern inputted from said input and output terminal portion (40), which inputs a signal outputted from said logic circuit portion (20) to said first signal path (108) and outputs it to said input and output terminal portion (40); and signal path switching circuit portions (50 and 51) disposed in the course of said first and said second signal paths (106, 107, 111; 106, 107, 110), respectively, which transmits the signal from said memory test input signal path (111) by switching off said first signal path (108) from said logic circuit portion (20), when said operation mode signal is at the memory test mode, and the signal from said output portion of said logic circuit testing signal memory circuit portion (80) by switching off said second signal path (106) from said memory portion (30), when said operation mode signal is at the logic circuit test mode.
Claim 11
Dependent Claim
56 words
A memory incorporating logic LSI according to Claim 7, wherein an input terminal, which applies a test signal from the exterior to said memory test input signal path (111), is used in common as an input terminal, through which a signal is inputted from the exterior to said logic circuit portion (20) at the usual operation.
Claim 12
Dependent Claim
55 words
A memory incorporating logic LSI according to Claim 7, wherein an output terminal, which outputs a signal from said memory test input signal path (111) to the exterior, is used in common as an input terminal, through which a signal is inputted from the exterior to said logic circuit portion (20) at the usual operation.
Claim 13
Dependent Claim
56 words
A memory incorporating logic LSI according to Claim 7, wherein an input terminal, which applies a test signal from the exterior to said memory test input signal path (111), is used in common as an output terminal, through which a signal is outputted from said logic circuit portion (20) to the exterior at the usual operation.
Claim 14
Dependent Claim
55 words
A memory incorporating logic LSI according to Claim 7, wherein an output terminal, which outputs a signal from said memory test input signal path (111) to the exterior, is used in common as an output terminal, through which a signal is outputted from said logic circuit portion (20) to the exterior at the usual operation.
Claim 15
Independent Claim
484 words
A method for testing a memory incorporating logic LSI including an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is trasmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a memory test input signal path (111), with which said input and output terminal portion (40) is connected and through which a signal for memory test is inputted and transmitted; a memory test output signal path (109), which outputs the output signal from said memory portion (30) to said input and output terminal portion (40); a logic circuit testing signal memory circuit portion (80) having an output portion outputting a predetermined logic circuit test pattern inputed from said input and output terminal portion (40), which inputs a signal outputted from said logic circuit portion (20) to said first signal path (108) and outputs it to said input and output terminal portion (40); and signal path switching circuit portions (50, 51) disposed in the course of said first and said second signal paths (106, 107, 111; 106, 107, 110), respectively, which transmits the signal from said memory test input signal path (111) by switching off said first signal path (108) from said logic circuit portion (20), when said opeation mode signal is at the memory test mode, and the signal from said output portion of said logic circuit testing signal memory circuit portion (80) by switching off said second signal path (106) from said memory portion (30), when said operation mode signal is at the logic circuit test mode, in order to test said memory portion (30) and said logic circuit portion (20), comprising the steps of: inputting said operation mode signal determining said operation mode of said memory incorporating logic LSI (10) so as to select either one of the memory test and the logic circuit test; switching over the signal path in said signal path switching circuit portions (50, 51); inputting a predetermined test signal from said input and output terminal portion (40); observing the result of the test effected by inputting said test signal in said input and output terminal portion (40); and comparing information obtained by observing said result with predetermined expected information.
Claim 16
Independent Claim
484 words
A method for testing a memory incorporating logic LSI including an input and output terminal portion (40), which transmits and receives input and output signals from and to the exterior; a memory portion (30), in and from which memory information is written and read out from and to the exterior through said input and output terminal portion (40); a logic circuit portion (20), which determines an output signal according to a predetermined logic, responding to said input signal; a first signal path (108, 109, 111), through which the signal is trasmitted from said logic circuit portion (20) to said memory portion (30); a second signal path (106, 107, 110), through which the signal is transmitted from said memory portion (30) to said logic circuit portion (20); operation mode input circuit portions (60, 61), which input an operation mode signal determining the operational state of said memory incorporating logic LSI (10) through said input and output terminal portion (40); a memory test input signal path (111), with which said input and output terminal portion (40) is connected and through which a signal for memory test is inputted and transmitted; a memory test output signal path (109), which outputs the output signal from said memory portion (30) to said input and output terminal portion (40); a logic circuit testing signal memory circuit portion (80) having an output portion outputting a predetermined logic circuit test pattern inputed from said input and output terminal portion (40), which inputs a signal outputted from said logic circuit portion (20) to said first signal path (108) and outputs it to said input and output terminal portion (40); and signal path switching circuit portions (50, 51) disposed in the course of said first and said second signal paths (106, 107, 111; 106, 107, 110), respectively, which transmits the signal from said memory test input signal path (111) by switching off said first signal path (108) from said logic circuit portion (20), when said opeation mode signal is at the memory test mode, and the signal from said output portion of said logic circuit testing signal memory circuit portion (80) by switching off said second signal path (106) from said memory portion (30), when said operation mode signal is at the logic circuit test mode, in order to test said memory portion (30) and said logic circuit portion (20), comprising the steps of: inputting said operation mode signal determining said operation mode of said memory incorporating logic LSI (10) so as to select either one of the memory test and the logic circuit test; switching over the signal path in said signal path switching circuit portions (50, 51); inputting a predetermined test signal from said input and output terminal portion (40); observing the result of the test effected by inputting said test signal in said input and output terminal portion (40); and comparing information obtained by observing said result with predetermined expected information.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.