EP0309995A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
System for fast selection of non-cacheable address ranges using programmed array logic
Assignee: Compaq Computer Corp
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Filing: 1988-09-27
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Granted: —
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Expires: 2008-09-27
Abstract
Abstract A fast logic system for decoding addresses for the purpose of designating areas of memory as non-cacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.
Inventors
- 👤 Paul R. Culley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 18:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0864; G06F12/0888
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
26 words
A computer system comprising a processor, a memory, a cache controller and means for selecting memory locations for cacheing within one read cycle of the processor.
Claim 2
Dependent Claim
26 words
A computer system comprising a processor, a memory, a cache controller and means for selecting memory locations for cacheing within one read cycle of the processor.
References Cited (Backward Citations)
No citation records indexed.
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