Vertical semiconductor device having a sidewall emitter

Claim 2

A vertical semiconductor device having a sidewall emitter which includes, a substrate (10); a first dielectric layer (14) on said substrate (10); a second dielectric layer (18); the invention being characterized by: a first polycrystalline semiconductor region (16) on said first dielectric layer (14), said first polycrystalline semiconductor region (16) including a doped portion for contacting an emitter (28) and acting as a diffusion source for said emitter (28); the second dielectric layer (18) being formed on said first polycrystalline semiconductor region (16); a first epitaxial region (24) extending from said substrate (10) through said first (14) and second (18) dielectric layers and said first polycrystalline semiconductor region (16), said epitaxial region (24) includes an emitter (28), a base (32) and a collector portion (30), and wherein said emitter portion (28) contacts said portion of said first polycrystalline semiconductor region (16) at a location between said first (14) and second (18) dielectric layers; and a plurality of contacts (38, 40, 42), said contacts (38, 40, 42) being electrically coupled to said emitter (28), said base (32) and said collector (30).

Claim 3

The device of claim 1 further including a second epitaxial region (26) electrically coupled to the collector (30) by a doped buried layer (12) in the substrate (10).

Claim 4

The device of claim 1 further comprising: a second polycrystalline semiconductor region (44) on the first dielectric layer (14); and a third dielectric layer (46) disposed between the first (16) and said second (44) polycrystalline semiconductor regions.

Claim 5

The device of claim 3 wherein said second polycrystalline semiconductor layer (44) contacts the collector portion (30) of said first epitaxial region (24).

Claim 6

The device of claim 3 wherein the dielectric layers (14, 18, 46) are comprised of oxide, nitride or combinations of oxide and nitride.

Claim 7

The device of claim 5 wherein the dielectric layers (14, 18, 46) comprise SiO₂.

Claim 8

A process for fabricating a vertical semiconductor device having a sidewall emitter made by the steps of, providing a substrate (10) ; forming a first dielectric layer (14) on said substrate (10) ; forming and doping a first polycrystalline semiconductor region (16) on said first dielectric layer (14); patterning and etching said first polycrystalline semiconductor region (16) in a predetermined manner to form at least one first polycrystalline island (16) ; forming a second dielectric layer (18) on said first polycrystalline island (16) ; forming a first opening (20), said first opening (20) extending to said substrate (10) through said dielectric layers (14, 18) and said first polycrystalline island (16); forming a first epitaxial region (24) in said first opening (20); the invention being characterized by the following steps: forming an emitter (28) in said first epitaxial region (24) in contact with said first polycrystalline island (16) exposed in said first epitaxial region (24). forming a base (32) and a collector (30) in said first epitaxial region (24); and forming a plurality of contacts (38, 40, 42), said contacts (38, 40, 42) being electrically coupled to said emitter, (28) said base (32) and said collector (30).

Claim 9

A process for fabricating a vertical semiconductor device having a sidewall emitter made by the steps of, providing a substrate (10) ; forming a first dielectric layer (14) on said substrate (10) ; forming and doping a first polycrystalline semiconductor region (16) on said first dielectric layer (14); patterning and etching said first polycrystalline semiconductor region (16) in a predetermined manner to form at least one first polycrystalline island (16) ; forming a second dielectric layer (18) on said first polycrystalline island (16) ; forming a first opening (20), said first opening (20) extending to said substrate (10) through said dielectric layers (14, 18) and said first polycrystalline island (16); forming a first epitaxial region (24) in said first opening (20); the invention being characterized by the following steps: forming an emitter (28) in said first epitaxial region (24) in contact with said first polycrystalline island (16) exposed in said first epitaxial region (24). forming a base (32) and a collector (30) in said first epitaxial region (24); and forming a plurality of contacts (38, 40, 42), said contacts (38, 40, 42) being electrically coupled to said emitter, (28) said base (32) and said collector (30).

Claim 10

The process of claim 7 further comprising the steps of: forming a doped buried layer (12) in the substrate (10). forming a second opening (22), said second opening (22) extending from said substrate (10) through the dielectric layers (14, 18); and forming a second epitaxial region (26) in said second opening (22), said second epitaxial region (26) having a conductivity type which corresponds to that of said buried layer (12).

Claim 11

The process of claim 7 further comprising the steps of: forming and doping a second polycrystalline semiconductor region (44) on the first dielectric layer (14); and forming a third dielectric layer (46) on said second polycrystalline semiconductor region (44), said third dielectric layer (46) disposed between the first (16) and second (44) polycrystalline semiconductor regions.

Claim 12

The process of claim 7 wherein the steps of forming dielectric layers (14, 18, 46) include forming said dielectric layers (14, 18, 46) of oxide, nitride or a combination of oxide and nitride.