EP0308152A2 — MIS integrated circuit device and method of manuf…

Claim 1

Independent Claim 126 words

A semiconductor device comprising: a semiconductor substrate (1) of first conductivity type; and MISFETs formed on said semiconductor substrate, each of the MISFETs being provided with: a gate electrode (8) which includes a P⁺-type polycrystalline silicon film; first semiconductor regions of second conductivity type opposite to the first conductivity type, which are formed in said semiconductor substrate (1) and which are source and drain regions, respectively, and a second semiconductor region (7) which is formed by introducing an N-type impurity into a part of said semiconductor substrate under said gate electrode and which is shallower than said first semiconductor region; wherein a threshold voltage of said each MISFET is controlled by said polycrystalline silicon film and the N-type impurity which forms said second semiconductor region (7).

Claim 2

Dependent Claim 126 words

A semiconductor device comprising: a semiconductor substrate (1) of first conductivity type; and MISFETs formed on said semiconductor substrate, each of the MISFETs being provided with: a gate electrode (8) which includes a P⁺-type polycrystalline silicon film; first semiconductor regions of second conductivity type opposite to the first conductivity type, which are formed in said semiconductor substrate (1) and which are source and drain regions, respectively, and a second semiconductor region (7) which is formed by introducing an N-type impurity into a part of said semiconductor substrate under said gate electrode and which is shallower than said first semiconductor region; wherein a threshold voltage of said each MISFET is controlled by said polycrystalline silicon film and the N-type impurity which forms said second semiconductor region (7).

Claim 3

Dependent Claim 80 words

A semiconductor device according to claim 1, wherein each of said first semiconductor regions (10,11) is constructed of a third semiconductor region (10B,11B) which is formed so as to be spaced from said gate electrode (8), and a fourth semiconductor region (10A,11A) which is formed between said gate electrode (8) and said third semiconductor region (10B,11B) and which is shallower than said third semiconductor region (10B,11B) and has an impurity concentration lower than that of said third semiconductor region (10B,11B).

Claim 4

Dependent Claim 50 words

A semiconductor device according to claim 1 or claim 2, wherein each of said MISFETs is further provided with side walls (12) which are formed on sides of said gate electrode (8), and the third semiconductor regions (10B,11B) are respectively spaced from said gate electrode by said side walls (12).

Claim 5

Dependent Claim 25 words

A semiconductor device according to any one of the preceding claims. wherein the N-type impurity is selected from the group consisting of As and Sb.

Claim 6

Dependent Claim 59 words

A semiconductor device according to any one of the preceding claims, wherein said gate electrode (8) is constructed of a double-layer film in which said P⁺-type polycrystalline silicon film (8A) is overlaid with a film (8B) of any refractory metal such as Mo, W, Ti, Ta and Pd, or a film of a silicide of such a refractory metal.

Claim 7

Dependent Claim 18 words

A semiconductor device according to any one of the preceding claims, wherein the first conductivity type is P-type.

Claim 8

Dependent Claim 19 words

A semiconductor device according to any one of claims 1 to 5, wherein the first conductivity type is N-type.

Claim 9

Dependent Claim 226 words

A semiconductor device comprising: a semiconductor substrate (1) of first conductivity type; a well region (2) of the first conductivity type and a well region (3) of second conductivity type, which are formed in said semiconductor substrate (1); and first and second groups of at least one MISFET which are formed on said semiconductor substrate, and each MISFET of which is provided with a gate electrode (8) which includes a P⁺-type polycrystalline silicon film, semiconductor regions (10,11) which are source and drain regions formed in said semiconductor substrate (1), respectively, and a first semiconductor region (7) which is formed by introducing an N-type impurity into a part of said semiconductor substrate (1) under said gate electrode (8), the N-type impurity of said first semiconductor region controlling the threshold voltages of each of the MISFETs conjointly with said P⁺-type polycrystalline silicon film, the first and second groups of said MISFETs being respectively formed in said well region (2) of the first conductivity type and said well region (3) of the second conductivity type; wherein one of the first and second groups consists of P-channel MISFETs, said semiconductor regions (11) of each of which are second semiconductor regions of P-type, and wherein the other of the first and second groups consists of N-channel MISFETs, said semiconductor regions (10) of each of which are third semiconductor regions of N-type.

Claim 10

Dependent Claim 226 words

A semiconductor device comprising: a semiconductor substrate (1) of first conductivity type; a well region (2) of the first conductivity type and a well region (3) of second conductivity type, which are formed in said semiconductor substrate (1); and first and second groups of at least one MISFET which are formed on said semiconductor substrate, and each MISFET of which is provided with a gate electrode (8) which includes a P⁺-type polycrystalline silicon film, semiconductor regions (10,11) which are source and drain regions formed in said semiconductor substrate (1), respectively, and a first semiconductor region (7) which is formed by introducing an N-type impurity into a part of said semiconductor substrate (1) under said gate electrode (8), the N-type impurity of said first semiconductor region controlling the threshold voltages of each of the MISFETs conjointly with said P⁺-type polycrystalline silicon film, the first and second groups of said MISFETs being respectively formed in said well region (2) of the first conductivity type and said well region (3) of the second conductivity type; wherein one of the first and second groups consists of P-channel MISFETs, said semiconductor regions (11) of each of which are second semiconductor regions of P-type, and wherein the other of the first and second groups consists of N-channel MISFETs, said semiconductor regions (10) of each of which are third semiconductor regions of N-type.

Claim 11

Dependent Claim 21 words

A semiconductor device according to claim 8, wherein the N-type impurity is selected from the group consisting of As and Sb.

Claim 12

Dependent Claim 59 words

A semiconductor device according to claim 8 or claim 9, wherein said gate electrode (8) is constructed of a double-layer film in which said P⁺-type polycrystalline silicon film (8A) is overlaid with a film (8B) of any of refractory metals such as Mo, W, Ti, Ta and Pd, or a film of a silicide of such a refractory metal.

Claim 13

Dependent Claim 84 words

A semiconductor device according to any one of claims 8 to 10, wherein said each second semiconductor region (10) is constructed of a fourth semiconductor region (10B) which is formed so as to be spaced from said gate electrode (8), and a fifth semiconductor region (10A) which is formed between said gate electrode (8) and said fourth semiconductor region (10B) and which is shallower than said fourth semiconductor region (10B) and has an impurity concentration lower than that of said fourth semiconductor region (10B).

Claim 14

Dependent Claim 83 words

A semiconductor device according to any of claims 8 to 11, wherein said each third semiconductor region (11) is constructed of a sixth semiconductor region (11B) which is formed so as to be spaced from said gate electrode (8), and a seventh semiconductor region (11A) which is formed between said gate electrode (8) and said sixth semiconductor region (11B) and which is shallower than said sixth semiconductor region (11B) and has an impurity concentration lower than that of said sixth semiconductor region (11B).

Claim 15

Dependent Claim 56 words

A semiconductor device according to claim 12 as appendant on claim 11, wherein each of the MISFETs is further provided with side walls (12) which are formed on sides of said gate electrode (8), and the fourth (10B) and sixth (11B) semiconductor regions are respectively spaced from the gate electrodes (8) by said side walls (12).

Claim 16

Independent Claim 435 words

A method of manufacturing a semiconductor device having N-channel MISFETs and P-channel MISFETs which are formed in a semiconductor substrate (1) of first conductivity type, one of the N-channel and P-channel MISFETs being formed within a well region (2,3) of the first conductivity type formed in the semiconductor substrate and the other of them being formed within a well region (3,2) of second conductivity type formed in the semiconductor substrate comprising: (a) the step of introducing an impurity of N-type into parts of a principal surface of said semiconductor substrate (1) for forming said N-channel and P-channel MISFETs, thereby to form first regions (7); (b) the step of depositing a polycrystalline silicon film (8A) for forming gate electrodes (8) of the respective MISFETs; (c) the step of introducing an impurity of P-type into said polycrystalline silicon film; (d) the step of depositing a film (8B) on the polycrystalline silicon into which the P-type impurity has been introduced, said film being a refractory metal film or a refractory metal silicide film, and then etching said films with photoresist masks, thereby to form said gate electrodes (8), each gate electrode (8) having two sides; (e) the step of introducing an impurity of the N-type into the region for forming said N-channel MISFETs, with said gate electrodes (8) as a mask, thereby to form second regions (10A); (f) the step of introducing an impurity of the P-type into the first region (7) for forming said P-channel MISFETs, with said gate electrodes (8) as a mask, thereby to form third regions (11A); (g) the step of forming side walls (12) on the respective sides of said each gate electrode (8); (h) the step of introducing an impurity of the N-type into the region for forming said N-channel MISFETs, with said gate electrodes (8) and said side walls (12) as a mask, thereby to form fourth regions (10B), the fourth regions (10B) being deeper than the second regions (10A) and having an impurity concentration higher than that of the second regions (10A) so as to construct source and drain regions of said N-channel MISFETs conjointly with said second regions (10A); and (i) the step of introducing an impurity of the P-type into the region for forming said P-channel MISFETs, with said gate electrodes (8) and said side walls (12) as a mask, thereby to form fifth regions (11B), the fifth regions (11B) being deeper than the third regions (11A) and having an impurity concentration higher than that of the third regions (11A) so as to construct source and drain regions of said P-channel MISFETs conjointly with said third regions (11A).

Claim 17

Independent Claim 435 words

A method of manufacturing a semiconductor device having N-channel MISFETs and P-channel MISFETs which are formed in a semiconductor substrate (1) of first conductivity type, one of the N-channel and P-channel MISFETs being formed within a well region (2,3) of the first conductivity type formed in the semiconductor substrate and the other of them being formed within a well region (3,2) of second conductivity type formed in the semiconductor substrate comprising: (a) the step of introducing an impurity of N-type into parts of a principal surface of said semiconductor substrate (1) for forming said N-channel and P-channel MISFETs, thereby to form first regions (7); (b) the step of depositing a polycrystalline silicon film (8A) for forming gate electrodes (8) of the respective MISFETs; (c) the step of introducing an impurity of P-type into said polycrystalline silicon film; (d) the step of depositing a film (8B) on the polycrystalline silicon into which the P-type impurity has been introduced, said film being a refractory metal film or a refractory metal silicide film, and then etching said films with photoresist masks, thereby to form said gate electrodes (8), each gate electrode (8) having two sides; (e) the step of introducing an impurity of the N-type into the region for forming said N-channel MISFETs, with said gate electrodes (8) as a mask, thereby to form second regions (10A); (f) the step of introducing an impurity of the P-type into the first region (7) for forming said P-channel MISFETs, with said gate electrodes (8) as a mask, thereby to form third regions (11A); (g) the step of forming side walls (12) on the respective sides of said each gate electrode (8); (h) the step of introducing an impurity of the N-type into the region for forming said N-channel MISFETs, with said gate electrodes (8) and said side walls (12) as a mask, thereby to form fourth regions (10B), the fourth regions (10B) being deeper than the second regions (10A) and having an impurity concentration higher than that of the second regions (10A) so as to construct source and drain regions of said N-channel MISFETs conjointly with said second regions (10A); and (i) the step of introducing an impurity of the P-type into the region for forming said P-channel MISFETs, with said gate electrodes (8) and said side walls (12) as a mask, thereby to form fifth regions (11B), the fifth regions (11B) being deeper than the third regions (11A) and having an impurity concentration higher than that of the third regions (11A) so as to construct source and drain regions of said P-channel MISFETs conjointly with said third regions (11A).

Claim 18

Dependent Claim 47 words

A method of manufacturing a semiconductor device according to claim 14, wherein the N-type impurity for forming the first regions (7) is As or Sb, and said first regions (7) are formed by ion-implanting said N-type impurity under conditions of 60 KeV and 5 x 10¹¹ atoms/cm².

Claim 19

Dependent Claim 29 words

A method of manufacturing a semiconductor device according to claim 14 or claim 15, wherein the P-type impurity which is introduced into said polycrystalline silicon film (8A) is boron.

Claim 20

Independent Claim 50 words

A method of manufacturing a semiconductor device according to any one of claims 14 to 16, wherein the N-type impurity for forming the fourth regions (10B) is As, and said fourth regions (10B) are formed by ion-implanting said N-type impurity under conditions of 80 KeV and 5 x 10¹⁵ atoms/cm².

Claim 21

Independent Claim 28 words

A method of manufacturing a semiconductor device according to any one of claims 14 to 17, wherein the P-type impurity for forming said fifth regions (11B) is boron.

MIS integrated circuit device and method of manufacturing the same

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