Data buffer apparatus and method

Claim 3

The method of operating a plurality of arrays of memory cells according to claim 1 characterized in that in the consecutive accessing, data signals are read or written during one interval in memory cells along one row thereof in one array independently of data signals that are read or written in memory cells along a row thereof in another array during another interval.

Claim 4

The method according to claim 1 characterized in that the address locations are counted in the arrays to which data signals are written; in that the address locations in the arrays from which data signals are read are counted; in that the counting range is extended to twice the number of address locations to be accessed to provide each address location in the arrays with two number designations in cyclic sequence; and in that output indications of the empty or full status of the arrays are produced in response to the relationships of counted rows of memory cells written in or read from.

Claim 5

The method of operating a plurality of arrays of memory cells according to claim 3 characterized in that an output indication of the empty condition of the arrays is produced in response to the binary number designation of the count of address locations read from equalling the binary number designation of the count of address locations written to.

Claim 6

The method of operating a plurality of arrays of memory cells according to claim 3 characterized in that an output indication of the full condition of the arrays is produced in response to the logic combination of the most significant bit of the binary number of the count of address locations read from not equalling the most significant bit of the binary number designation of the count of address locations written to and all other bits of the binary numbers of the counts of address locations read from and written to being equal.

Claim 7

The method of operating a plurality of arrays of memory cells according to claim 5 characterized in that an output indication of the half full condition of the array is produced as the logic combination of the not-empty condition of the arrays and the next-most significant bit of the difference between the binary number of the count of address locations written to and the binary number of the count of the address locations read from.

Claim 8

Data storage apparatus particularly for performing the method of claim 1 , including a plurality of memory cells for storing data signals therein arranged in at least first and second arrays, each array having the memory cells arranged in rows and columns and requiring signal conditioning in an interval prior to reading or writing data therein and having cell control lines arranged in rows for controlling the reading and writing of data signals in selected cells within a row in response to activation of the cell control lines for the cells in a selected row characterized in that each memory cell has dual data access ports arranged in columns; in that row controllers are connected to all of the memory cells in each corresponding row in all of the arrays for selectively activating the cell control lines of all of the memory cells in the row; in that column controllers are connected to the memory cells in each array for selectively activating the data access ports of all of the memory cells in a selected column within an array for accessing the memory cell in the row and column at which the data access port and cell control lines are activated; in that driver circuits are connected to supply data signals to an accessed memory cell; in that sensing curcuits are connected to read data signals from an accessed memory cell; and in that control circuits are coupled to the row controllers and to the column controllers to maintain the cell control line of all of the memory cells in a selected row in all arrays simultaneously activated as the corresponding data access ports for the memory cells in an array are sequentially activated to read or write data signals in the memory cells accessed along the selected row of one array as the memory cells along the selected row in another array are conditioned for access in a subsequent interval.

Claim 9

Data storage apparatus according to claim 7 characterized in that the dual data access ports for each memory cell include first and second pairs of bit lines and first and second word lines for conditioning and operating the memory cell to read or write data signals therein in response to the potentials on the pairs of bit lines and on the word lines; and in that data signals on a first pair of bit lines are written in memory cells after conditioning in response to the potential on the first word line; and in that data signals in a memory cell are read on a second pair of bit lines after conditioning in response to the potential on the second word line.

Claim 10

Data storage apparatus according to claim 7 characterized in that said control circuits include read counters connected to the row controllers and sensing circuits, and write counters connected to the row controller and driver circuits for identifying by counter states the selected activated rows and columns of memory cells that are accessed for reading and writing data signals therein, said read counters and write counters including extended range of counting states equal to twice the number of address locations to be accessed to provide each address location in the arrays with two number designations in cyclic sequence; in that logic circuits are coupled to the read and write counters for producing output indications of the empty or full status of the arrays in response to the relationships of counter states of the read and writer counters.

Claim 11

Data storage apparatus according to claim 9 characterized in that said logic circuits produce an output indication of the empty condition of the array in response to the binary number designation of the read counter equalling the binary number designation of the write counter.

Claim 12

Data storage apparatus according to claim 9 characterized in that said logic circuits produce an output indication of the full condition of the array in response to the logic combination of the most significant bit of the binary number of the read counters not equalling the most significant bit of the binary number designation of the write counters and all other bits of the binary number of the read counters and write counters are equal.

Claim 13

Data storage apparatus according to claim 10 characterized in that said logic circuits produce an output indication of the half full condition of the array as the logic combination of the not-empty condition of the array and the next-most significant bit of the difference between the binary number of the write counters and the binary number of the read counters.

Claim 14

Data storage apparatus particularly for performing the method of claim 1 , including a plurality of memory cells arranged in matrix array of columns and independently addressable rows, characterized in that the rows are successively address numbered in cyclic order providing two address numbers per row; in that row controllers are connected to all of the memory cells in each corresponding row in the array for selectively accessing all of the memory cells in a selected row; in that read counters and write counters are connected to the row controllers for identifying by counter states the selected rows and columns of memory cells accessed for reading or writing data therein, each of said read counters and write counters including extended range of counting states equal to twice the number of address locations for independently accessing each row of memory cells in the array through two address numbers in cyclic sequence; and in that logic circuits are coupled to the read counters and to the write counters for producing output indications of the empty or full status of the arrays in response to the relationships of counter states of the read counters and write counters.

Claim 15

Data storage apparatus according to claim 13 characterized in that said logic circuits produce an output indication of the empty condition of the array in response to the binary number designation of the read counters equalling the binary number designation of the write counters.

Claim 16

Data storage apparatus according to claim 13 characterized in that said logic circuits produce an output indication of the full condition of the array in response to the logic combination of the most significant bit of the binary number of the read counters not equalling the most significant bit of the binary number designation of the write counters and all other bits of the binary numbers of the read counters and write counters being equal.

Claim 17

Data storage apparatus according to claim 14 characterized in that said logic circuits produce an output indication of the half full condition of the array as the logic combination of the not-empty condition of the array and the nex-most significant bit of the difference between the binary number of the write counters and the binary number of the read counters.

Claim 18

Data signal circuitry particularly for performing the method of claim 1 including first and second gain elements of complementary conductivity types, each having first and second electrodes forming a data signal output circuit and having second and third electrodes forming a data signal input circuit with the data signal output circuits of the gain elements coupled to a data output, characterized by capacitors connected across the data signal input circuit of each of the gain elements; and by sources of currents to selectively charge the capacitors; and by switching circuits coupled to receive the currents from the sources and responsive to an applied data signal for selectively charging the capacitors to control the rate of change of data signal in said output circuit of each gain element.

Claim 19

Data signal circuitry according to claim 17 characterized in that said switching circuits include a first pair of complementary conductivity type transistors having control electrodes connected in common to receive the applied data signal, and a second pair of complementary conductivity type transistors having control electrodes connected in common to receive the applied data signal, each of said first and second pairs of transistors have output electrodes connected in common to a respective capacitor and in that said sources of currents are connected to the output electrodes of the first and second pairs of transistors for selectively supplying currents therethrough to the respective capacitors in response to conduction of one of said pair of transistors; and in that the other of each of said pairs of first and second transistors is connected to discharge the respective capacitors in response to conduction of such other transistor of the pair