EP0306020A2
Expired / Lapsed
EP
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Error correction coding and decoding circuit for digitally coded information
Assignee: Nippon Conlux Co Ltd
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Filing: 1988-09-01
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Granted: —
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Expires: 2008-09-01
Abstract
Abstract An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of the circuit, a data load clock signal for loading data onto the circuit, and a data read clock signal for reading data from the circuit are delivered from an external circuit provided separately from the error correction coding and decoding circuit.
Inventors
- 👤 Koichi Yamazaki
- 👤 Yasuyuki Kimura
- 👤 Osamu Yamada
- 👤 Toru Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 07:37
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/33; H03M13/37; H03M13/43
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
113 words
An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of said error correction coding and decoding circuit, a data load clock signal (CLKL) for loading data onto said error correction coding and decoding circuit, and a data read clock signal (CLKR) for reading data from said error correction coding and decoding circuit are delivered from an external circuit provided separately from said error correction coding and decoding circuit.
Claim 2
Dependent Claim
113 words
An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of said error correction coding and decoding circuit, a data load clock signal (CLKL) for loading data onto said error correction coding and decoding circuit, and a data read clock signal (CLKR) for reading data from said error correction coding and decoding circuit are delivered from an external circuit provided separately from said error correction coding and decoding circuit.
Claim 3
Dependent Claim
53 words
An error correction coding and decoding circuit for digitally coded information as set forth in claim 1, wherein said error correction coding and decoding circuit outputs a busy signal (BUSY) indicating that data load is inhibited, and signals indicative of an information section and a parity section at the time of reading data.
Claim 4
Dependent Claim
43 words
An error correction coding and decoding circuit for digitally coded information as set forth in claim 1, wherein said error correction coding and decoding circuit always outputs data after error correction at the same timing in accordance with a signal from the external.
Claim 5
Dependent Claim
70 words
An error correction coding and decoding circuit for digitally coded information as set forth in claim 1, wherein said clock signal (CLKC) for the internal operation of the circuit, said data load clock signal (CLKL) for loading data onto said error correction coding and decoding circuit, and said data read clock signal (CLKR) for reading data from said error correction coding and decoding circuit having different frequencies from each other.
Claim 6
Dependent Claim
68 words
An error correction coding and decoding circuit for digitally coded information as set forth in claim 1, wherein said clock signal (CLKC) for the internal operation of the circuit, said data load clock signal (CLKL) for loading data onto said error correction coding and decoding circuit, and said data read clock signal (CLKR) for reading data from said error correction ding and decoding circuit have the same frequencies.
Claim 7
Dependent Claim
34 words
An error correction coding and decoding circuit for digitally coded information as set forth in claim 1, wherein said error correction coding and decoding circuit is a circuit for dealing with code (272, 190).
Claim 8
Dependent Claim
37 words
An error correction coding and decoding circuit for digitally coded information as set forth in claim 1, wherein said error correction coding and decoding circuit is a circuit for dealing with codes except for code (272, 190).
References Cited (Backward Citations)
No citation records indexed.
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