An automatic test process for logic devices

Claim 2

A process according to Claim 1 further comprising performing a preprocessing step (5) of a state description of the device under test to obtain the said Boolean state equations.

Claim 3

A process according to Claim 2 characterised in that the preprocessing step (5) includes applying DeMorgan's theorem to the said Boolean state equations to derive the complements of the said Boolean state equations and to obtain minimised logic true and minimised logic false device state equations.

Claim 4

A process according to Claim 2, characterised in that the preprocessing step (5) includes applying consensus to the said Boolean state equations based upon the theorem xy + xz = xy + xz + yz to derive additional Boolean products to determine if necessary but not sufficient conditions exist for testing said device.

Claim 5

A process according to Claim 2, characterised in that the preprocessing step (5) includes deriving Boolean state equations which describe devices having asynchronous features such as register set, clear, clock and enable.

Claim 6

A process according to Claim 1 characterised in that the preprocessing step (5) includes adapting the said Boolean state equations to the topology of the device under test as it appears in a circuit as a result of inputs of the said device being tied to a predetermined state.

Claim 7

A process according to any preceding Claim characterised in that the step (10) of determining fault detection Boolean products comprises; selecting a primary Boolean product from the minimised logic true and minimised logic false device state equations which contains an input to be tested; defining all Boolean products of the device state equation other than the said primary Boolean product as secondary Boolean products; applying DeMorgan's theorem to the said secondary Boolean products to produce an expression defining a condition where the secondary Boolean products are logically false; and minimising the expression to obtain a set of minimised secondary Boolean products.

Claim 8

A process according to any of Claims 1 to 3, characterised in that the step of deriving the said initialisation sequences comprises: generating predecessor states by performing a Boolean AND operation with the minimised logic true and minimised logic false device state equations of a successor state to obtain a predecessor Boolean expression which meets conditions defined by output assignments of successor states; and eliminating redundant terms from the said predecessor Boolean expression.

Claim 9

A process according to Claim 8, characterised in that the step of eliminating redundant terms comprises eliminating terms from the said predecessor Boolean expression having output assignments corresponding to and covered by output assignments of Boolean expressions for successor states.

Claim 10

A process according to Claim 9, characterised in that it includes the step of applying consensus to the said predecessor Boolean expression using the theorem xy + /xz = xy + /xz + yz to obtain an expanded predecessor Boolean expression.

Claim 11

A process according to Claim 7, characterised in that the step of determining (10) fault detection Boolean products describing a state where the fault detection equations are true comprises: deriving a primary product vector from the said primary Boolean product: representing the minimised secondary Boolean products as secondary product vectors; and intersecting the said primary product vector with the said secondary product vectors to obtain a set of fault detection vectors describing a state where the fault detection equations are true.

Claim 12

A process according to Claim 11, characterised in that it further comprises applying consensus to output assignments of said set of fault detection vectors to derive additional set of fault detection vectors.

Claim 13

A process according to Claim 12 characterised in that the step of deriving initialisation sequences (12, 12, 14, 16, 17) comprises sequentially determining predecessor states (12) by selecting a predetermined fault detection vector from the said additional set of fault detection vectors for deriving an initialisation sequence; determining output assignments (12) of the said predetermined fault detection vector, performing a Boolean AND operation on the said minimised logic true and minimised logic false device state equations of a successor state to obtain a set of predecessor state notices, minimising the set of predecessor state nodes by eliminating redundant predecessor state nodes, applying a process of consensus base on the theorem xy + /yz = xy + /xz + yz to obtain an expanded set of predecessor state nodes, eliminating nodes of the predecessor states using the process of pruning by reducing the said reduced set of predecessor state nodes by eliminating nodes that have redundant output assignments derived from said predetermined fault detection vector to obtain a further reduced set of predecessor state nodes, reducing the said reduced set of predecessor state nodes with respect to covered output assignments based on the theorem x + xy = x to obtain a further reduced set of predecessor state nodes, reducing the said further reduced set of predecessor state nodes by eliminating nodes derived from any other fault detection vector of said set of fault detection vectors for which no initialisation sequence exists, and continuing a process of sequentially determining the said predecessor states and eliminating nodes of the said predecessor states to obtain the said initialisation sequence.