Active matrix cell and method of manufacturing the same

Claim 2

An active matrix cell using a thin-film field effect transistor (3) of a top gate staggered structure including a first conductor group (102) constituting a source and a drain (6), a semiconductor film (103a), a first insulating film (103 b) serving as a gate insulating film and a second conductor group (105) including a gate electrode, all of which are formed on a substrate (100) in the order named, wherein said semiconductor film (103a) and said first insulating film (103b) have the same area and constitute a two-layered region (103A), a second insulating film (104) having substantially the same thickness as that of said two-­layered region (103A) is formed in contact with a side surface of said two-layered region (103A) under at least said gate electrode, and said gate electrode is present on said first insulating film (103b) and said second insulating film (104).

Claim 3

An active matrix cell according to claim 1, wherein there is used a wiring intersection portion including a first conductor included in said first conductor group (102), said semiconductor film (103a), said first insulating film (103b), a second conductor included in said second conductor group (105), all of which are formed on said substrate (100) in the order named, said wiring intersection portion (7) being arranged such that said semiconductor film (103a) and said first insulating film (103b) have the same area and constitute a two-layered region (103B), said second insulating film (104) having substantially the same thickness as that of said two-layered region (103B) is formed in contact with said side surface of said two-layered region (103B) under at least said second conductor (105), and said second conductor (105) is on said first insulating film (103b) and said second insulating film (105).

Claim 4

A cell according to claim 1 or 2, wherein said cell uses a thin-film field effect transistor including a third insulating film (200; 300) having substantially the same thickness as that of said first conductor group (102), said third insulating film (200; 300) being formed around said first conductor group (102) so as to be in contact with said first conductor group (102).

Claim 5

An active matrix cell using a wiring intersection portion (7) including a first conductor (102), a semiconductor film (103a), a first insulating film (103b), a second conductor (105), all of which are formed on a substrate (100) in the order named, said wiring intersection portion (7) being arranged such that said semiconductor film (103a) and said first insulating film (103b) have the same area and constitute a two-layered region (103B), a second insulating film (104) having substantially the same thickness as that of said two-layered region (103B) is formed in contact with a side surface of said two-layered region under at least said second conductor, and said second conductor (105) is on said first insulating film (103b) and said second insulating film (104).

Claim 6

An active matrix cell using a wiring intersection portion (7) including a first conductor (102), a semiconductor film (103a), a first insulating film (103b), a second conductor (105), all of which are formed on a substrate (100) in the order named, said wiring intersection portion (7) being arranged such that said semiconductor film (103a) and said first insulating film (103b) have the same area and constitute a two-layered region (103B), a second insulating film (104) having substantially the same thickness as that of said two-layered region (103B) is formed in contact with a side surface of said two-layered region under at least said second conductor, and said second conductor (105) is on said first insulating film (103b) and said second insulating film (104).

Claim 7

A cell according to any of the claims 2 to 4, wherein said wiring intersection portion (7) includes a third insulating film (200; 300) having substantially the same thickness as that of said first conductor, said third insulating film (200; 300) being formed around said first conductor so as to be in contact with said first conductor group (102).

Claim 8

An active matrix cell comprising: - a first conductor group (102) formed on a transparent substrate (100) and constituting a source (5) and a drain (6) of a field effect thin-film transistor (3), part of a data line (1), and a pixel electrode (4); - two-layered regions (103A, 103B) formed on said transparent substrate (100) and being formed of a semiconductor film (103a) and a first insulating film (103b) which is formed on said semiconductor film (103a) and an area of said first insulating film (103b), in said two-­ layered regions (103A,103B) has substantially the same area as that of said semiconductor film (103a); - a second insulating film (105) contacting a side surface of said two-layered regions (103A,103B), having substantially the same thickness as that of said two-layered regions, and covering a region excluding said two-layered regions and said first conductor group (102); and - a second conductor group (105) serving as a scanning line (2) and part of said data line (1), wherein one (103A) of said two-layered regions connects said source (5) and said drain (6), partially overlaps said source and said drain so as to serve as an active region of said thin-film transistor (3), and the other (103B) of said two-layered regions overlaps said data line (1) so as to have an area larger than an area defined by widths of adjacent ones of said data (1) and scanning lines (2) at an intersection region (7) between said data and scanning lines, and a second conductor included in said second conductor group (105) serving as said scanning line (2) partially overlaps said source (5) and said drain (6) therebetween on said two-layered region (103A) serving as the active region of said thin-film transistor so as to have a width larger than a distance between said source (5) and said drain (6), and the other conductors included in said second conductor group (105) are insulated from said scanning line.

Claim 9

An active matrix cell comprising: - a first conductor group (102) formed on a transparent substrate (100) and constituting a source (5) and a drain (6) of a field effect thin-film transistor (3), part of a data line (1), and a pixel electrode (4); - two-layered regions (103A, 103B) formed on said transparent substrate (100) and being formed of a semiconductor film (103a) and a first insulating film (103b) which is formed on said semiconductor film (103a) and an area of said first insulating film (103b), in said two-­ layered regions (103A,103B) has substantially the same area as that of said semiconductor film (103a); - a second insulating film (105) contacting a side surface of said two-layered regions (103A,103B), having substantially the same thickness as that of said two-layered regions, and covering a region excluding said two-layered regions and said first conductor group (102); and - a second conductor group (105) serving as a scanning line (2) and part of said data line (1), wherein one (103A) of said two-layered regions connects said source (5) and said drain (6), partially overlaps said source and said drain so as to serve as an active region of said thin-film transistor (3), and the other (103B) of said two-layered regions overlaps said data line (1) so as to have an area larger than an area defined by widths of adjacent ones of said data (1) and scanning lines (2) at an intersection region (7) between said data and scanning lines, and a second conductor included in said second conductor group (105) serving as said scanning line (2) partially overlaps said source (5) and said drain (6) therebetween on said two-layered region (103A) serving as the active region of said thin-film transistor so as to have a width larger than a distance between said source (5) and said drain (6), and the other conductors included in said second conductor group (105) are insulated from said scanning line.

Claim 10

An active matrix cell comprising data (1) and scanning lines (2) arranged in a matrix form, a pixel electrode (4), and a field effect thin-film transistor (3), an output electrode (6) of which is connected to said pixel electrode, the other output electrode (5) of which is connected to said data line, and an input electrode of which is connected to said scanning line, said data (1) and scanning lines (2), said pixel electrode (4), and said field effect thin-film transistor (3) being formed on a transparent substrate (100) in a predetermined pattern, wherein said data line (1) has a two-layered structure; said output electrode (5) of said field effect thin-film transistor (3), a lower layer (1) of said two-layered structure of said data line, and said pixel electrode (4) are constituted by a first conductor group (102); said field effect thin-film transistor includes a two-layered region (103A) which partially overlaps said output electrodes (5, 6) apart from each other and serves as an active region of said transistor, said two-layered region (103A) consists of semiconductor (103a) placed on said substrate (100) and first insulator (103b) which has the same area as that of said semiconductor, said two-layered region (103A) being provided with a side surface contacting a second insulating film (104), said second insulating film covering a region excluding said two-layered region (103A) and said first conductor group (102), and the other two-layered region (103B) which has the same structure as that of said two-­layered region overlaps said data line (1) so as to have an area larger than an area defined by widths of adjacent ones of said data (1) and scanning lines (2); and said scanning line is constituted by one second conductor group (105), said scanning line including a gate electrode of said transistor (3) which partially overlaps said output electrodes (5, 6) on said two-layered region (103A) serving as the active region of said transistor so as to have a width larger than a distance between said output electrodes (5, 6) and said second conductor group (105), a portion of which serves as part of said data line (1), being insulated from said scanning line (2).

Claim 11

An active matrix cell comprising data (1) and scanning lines (2) arranged in a matrix form, a pixel electrode (4), and a field effect thin-film transistor (3), an output electrode (6) of which is connected to said pixel electrode, the other output electrode (5) of which is connected to said data line, and an input electrode of which is connected to said scanning line, said data (1) and scanning lines (2), said pixel electrode (4), and said field effect thin-film transistor (3) being formed on a transparent substrate (100) in a predetermined pattern, wherein said data line (1) has a two-layered structure; said output electrode (5) of said field effect thin-film transistor (3), a lower layer (1) of said two-layered structure of said data line, and said pixel electrode (4) are constituted by a first conductor group (102); said field effect thin-film transistor includes a two-layered region (103A) which partially overlaps said output electrodes (5, 6) apart from each other and serves as an active region of said transistor, said two-layered region (103A) consists of semiconductor (103a) placed on said substrate (100) and first insulator (103b) which has the same area as that of said semiconductor, said two-layered region (103A) being provided with a side surface contacting a second insulating film (104), said second insulating film covering a region excluding said two-layered region (103A) and said first conductor group (102), and the other two-layered region (103B) which has the same structure as that of said two-­layered region overlaps said data line (1) so as to have an area larger than an area defined by widths of adjacent ones of said data (1) and scanning lines (2); and said scanning line is constituted by one second conductor group (105), said scanning line including a gate electrode of said transistor (3) which partially overlaps said output electrodes (5, 6) on said two-layered region (103A) serving as the active region of said transistor so as to have a width larger than a distance between said output electrodes (5, 6) and said second conductor group (105), a portion of which serves as part of said data line (1), being insulated from said scanning line (2).

Claim 12

A cell according to claim 8 or 9, wherein a third insulating film (200, 300) having substantially the same thickness as that of said first conductor group (102) is formed around said first conductor group so as to contact said first conductor group.

Claim 13

A cell according to claims 1 to 8, wherein said semiconductor layer (103a) consists of amorphous silicon.

Claim 14

A cell according to claims 1 to 8, wherein said semiconductor layer (103a) consists of polysilicon.

Claim 15

A cell according to claims 1 to 10, wherein said first conductor group (102) includes a transparent conductor, an opaque conductor formed on said transparent conductor, and an n-type semiconductor serving as an uppermost layer.

Claim 20

A method according to claim 12 or 13, further comprising the steps of: applying said negative insulating photosensitive resin after the step of forming said first conductive group, exposing said photosensitive resin from said back side of said transparent substrate by using said first conductor group as a light-shielding mask, developing the photosensitive resin, and forming a third insulating film of said photosensitive resin in a region excluding said first conductor group, said third insulating film having substantially the same thickness as that of said first conductor group.