EP0303363A2
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EP
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Echo canceller
Assignee: Telent Technologies Services Ltd
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Filing: 1988-07-22
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Granted: —
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Expires: 2008-07-22
Abstract
Abstract An echo canceller (1) for full duplex digital data transmission in a transmitter/receiver unit when connected via a hybrid circuit (2) to one end of a two wire line (3). In order to provide adequate cancellation at a line data rate of 160 kbit/s over 7-8 km, a data bit history of at least 9 bits is used to address a memory having at least 3 partitions (41-44) with the first partition (41) being addressed by a sequence of at least 3 data bits. This partitioning achieves a small memory size, less than 2 kbits, and a small total chip area for integrated circuit realisation of the canceller together with a clocking speed for moderate power consumption is maintained by using serial arithmetic (61-63) for adding the partition outputs together with pipelining (D1, D21 - D24). An exponentially quantitising analogue-to-digital converter error signal circuit (9), shown in detail in Figure 2, is used which has wider application to echo cancellers other than the partitioned memory compensation type.
Inventors
- 👤 Ian Juso Dedic
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 16:14
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/02; H04B3/20; H04B3/23; H04B3/231
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
430 words
An echo canceller (1) for enabling full duplex digital data communication in a transmitter/receiver unit when connected via a hybrid circuit (2) to one end of a two-wire line (3), in which a memory unit (4) has memory partitions (41-44) each of which is addressed by a sequence of data bits transmitted over part of a predetermined data interval, in which once per sample period there is directly read from each memory partition (41-44) a digital estimate of the near end echo of the data transmitted over a corresponding part of said data interval, in which the memory unit (4) said digital estimates read at the same time are added to provide a digital estimate of the full near end echo of the data transmitted over said data interval, in which each said digital full echo estimate is applied via a digital-to-analogue converter (7) to an analogue summation circuit (8) together with the received signal to suppress said near end echo in the received signal, and in which an error signal circuit (9) derives from the output of the analogue summation circuit an error signal which is applied to the memory unit (4) such that once per sample period an error adjusted digital estimate is written into each memory partition (41-44), characterised in that there are at least three memory partitions (41-44), the one which is addressed by the most recently transmitted data being addressed by a sequence of at least three data bits and said data interval being at least nine data bit periods, in that the addition of digital estimates from the memory partitions is by a serial arithmetic arrangement (61-63), each full echo estimate being applied to the analogue summation circuit (8) at an integral number of sample periods after the corresponding digital estimates are read from the memory partitions (41-44), in that the near end echo path for the transmitted data includes means (D1) which delay the near end echo so that each full echo estimate is applied to the analogue summation circuit (8) together with the near end echo which it is intended to suppress, and in that means (D21-D24) are provided in the memory unit to apply each digital estimate read from a memory partition (41-44) to an error adder (64-67) provided in respect of that partition such that each error signal is applied to a said error adder (64-67) together with the digital estimate which it is intended to adjust, each adjusted digital estimate being written into its respective memory partition (41-44) an integral number of sample periods after it was read therefrom.
Claim 2
Dependent Claim
430 words
An echo canceller (1) for enabling full duplex digital data communication in a transmitter/receiver unit when connected via a hybrid circuit (2) to one end of a two-wire line (3), in which a memory unit (4) has memory partitions (41-44) each of which is addressed by a sequence of data bits transmitted over part of a predetermined data interval, in which once per sample period there is directly read from each memory partition (41-44) a digital estimate of the near end echo of the data transmitted over a corresponding part of said data interval, in which the memory unit (4) said digital estimates read at the same time are added to provide a digital estimate of the full near end echo of the data transmitted over said data interval, in which each said digital full echo estimate is applied via a digital-to-analogue converter (7) to an analogue summation circuit (8) together with the received signal to suppress said near end echo in the received signal, and in which an error signal circuit (9) derives from the output of the analogue summation circuit an error signal which is applied to the memory unit (4) such that once per sample period an error adjusted digital estimate is written into each memory partition (41-44), characterised in that there are at least three memory partitions (41-44), the one which is addressed by the most recently transmitted data being addressed by a sequence of at least three data bits and said data interval being at least nine data bit periods, in that the addition of digital estimates from the memory partitions is by a serial arithmetic arrangement (61-63), each full echo estimate being applied to the analogue summation circuit (8) at an integral number of sample periods after the corresponding digital estimates are read from the memory partitions (41-44), in that the near end echo path for the transmitted data includes means (D1) which delay the near end echo so that each full echo estimate is applied to the analogue summation circuit (8) together with the near end echo which it is intended to suppress, and in that means (D21-D24) are provided in the memory unit to apply each digital estimate read from a memory partition (41-44) to an error adder (64-67) provided in respect of that partition such that each error signal is applied to a said error adder (64-67) together with the digital estimate which it is intended to adjust, each adjusted digital estimate being written into its respective memory partition (41-44) an integral number of sample periods after it was read therefrom.
Claim 3
Dependent Claim
16 words
An echo canceller as claimed in Claim 1, in which there are four memory partitions (41-44).
Claim 4
Dependent Claim
28 words
An echo canceller as claimed in Claim 2, in which said serial arithmetic arrangement for adding the digital estimates from the memory partitions comprises three one-bit adders (61-63).
Claim 5
Dependent Claim
25 words
An echo canceller as claimed in Claim 2 or Claim 3, in which each memory partition is addressed by a sequence of three data bits.
Claim 6
Dependent Claim
41 words
An echo canceller as claimed in any one of Claims 1 to 4, in which there are four sample periods per data bit period and correspondingly four different digital estimates are read from each memory partition (41-44) per data bit period.
Claim 7
Dependent Claim
27 words
An echo canceller as claimed in any one of Claims 1 to 5, in which each digital estimate is a word consisting of at least twelve bits.
Claim 8
Dependent Claim
62 words
An echo canceller as claimed in any one of Claims 1 to 6, in which said means (D1) which delay the near end echo comprise means which delay the transmission of each data bit via the hybrid circuit (2) by an integral number of sample periods after that data bit is applied to the memory unit for addressing the memory partitions (41-44).
Claim 9
Dependent Claim
61 words
An echo canceller as claimed in any one of Claim 1 to 7, in which said digital estimates read from the memory partitions (41-44) at the same time are added by said serial arithmetic arrangement (61-63) in one sample period, and in which the resulting digital full echo estimate is converted by said digital-to-analogue converter (7) in the succeeding sample period.
Claim 10
Dependent Claim
81 words
An echo canceller as claimed in any one of Claims 1 to 8, in which said means provided to apply each digital estimate to an error adder consists of delay means (D21-D24) into which the bits of the digital estimate are input in serial form at the same time as they are put into said serial arithmetic arrangement (61-63) and from which the bits of that digital estimate are output in serial form delayed by an integral number of sample periods.
Claim 11
Dependent Claim
91 words
An echo canceller as claimed in any one of Claims 1 to 9, in which a serial/parallel register (412) is provided in respect of each memory partition (41-44), a digital estimate which has been read from that memory partition in parallel form being output from that register (412) in serial form to the serial arithmetic arrangement (61-63) while an adjusted digital estimate which is to be written into that memory partition (41-44) in parallel form is being input to that register (412) in serial form from the respective error adder (64-67).
Claim 12
Dependent Claim
46 words
An echo canceller as claimed in any one of Claims 1 to 10, in which the error signal circuit (9) is an analogue-to-digital converter which converts a sampled output of the analogue summation circuit to a digital error signal over an integral number of sample periods.
Claim 13
Dependent Claim
35 words
An echo canceller as claimed in Claim 11, in which both the digital error signal and each digital estimate which it is intended to adjust are applied in serial form to the respective error adder.
Claim 14
Dependent Claim
109 words
An echo canceller as claimed in Claim 11, in which the digital error signal is exponentially quantised, in which in the analogue-to-digital converter (9) the sampled output (SH) of the analogue summation circuit (8) is applied as an input voltage to charge a capacitor arrangement (C1-C3) to an initial voltage which is compared with a reference voltage (V R ) to provide a least significant bit output of the converter, after which in each of successive steps the voltage on the capacitor arrangement (C1-C3) is halved and that halved voltage is compared with said reference voltage (V R ) to provide the next significant bit output of the converter.
Claim 15
Dependent Claim
71 words
An echo canceller as claimed in Claim 13, in which each digital estimate which it is intended to adjust is applied to the respective error adder (64-67) in serial form, and in which the digital error signal is produced in one sample period, the bits of each digital error signal being applied to the error adders as they are produced in serial form without waiting for that signal to be completed.
Claim 16
Dependent Claim
132 words
An echo canceller as claimed in Claim 13, in which the analogue-to-digital converter (9) includes a single comparator (COMP) and a switching arrangement (SW1-SW3) by means of which said input voltage is first applied to the comparator (COMP) to determine the sign of that input voltage and to provide an output bit of the converter indicative of the sign, said reference voltage (V R and said initial voltage on the capacitor arrangement (C1-C3) then being applied in dependence on said determined sign of the input voltage to appropriate inputs of the comparator (COMP) to provide said least significant and succeeding output bits of the converter, and in which said sign bit and said least significant and succeeding bits are combined to provide the result of analogue-to-digital conversion in a predetermined bipolar code.
Claim 17
Dependent Claim
75 words
An echo canceller as claimed in Claim 15, in which each error adder (64-67) is a one-bit adder, in which the digital estimates are applied to the one-bit error adders in two's complement coded serial form, and in which the combination of the error signal least significant and succeeding bits with the error signal sign bit is performed by the one-bit adders (64-67) to provide the result of analogue-to-digital conversion in two's complement coded form.
Claim 18
Dependent Claim
288 words
An echo canceller (1) for enabling full duplex digital data communication in a transmitter/receiver unit when connected via a hybrid (2) circuit to one end of a two-wire line (3), in which a compensation unit (4) is addressed by a sequence of data bits transmitted over a predetermined data interval, in which the compensation unit (4) contains information from which is each of a number of sample periods per data bit period there is provided a digital estimate of the near end echo of the data transmitted over said data interval, in which each said digital estimate is applied via a digital-to-analogue converter (7) to an analogue summation circuit (8) together with the received signal to suppress said near end echo in the received signal, and in which an error signal circuit (9) derives from the output of the analogue summation circuit an error signal which is applied to the compensation unit (4) such that once per sample period the information in the compensation unit is adjusted, characterised in that the error signal circuit (9) is an analogue-to-digital converter which converts a sampled output of the analogue summation circuit to an exponentially quantised digital error signal, and in that in the analogue-to-digital converter the sampled output (SH) of the analogue summation circuit (8) is applied as an input voltage to charge a capacitor arrangement (C1-C3) to an initial voltage which is compared with a reference voltage (V R ) to provide at least significant bit output of the converter, after which in each of successive steps the voltage on the capacitor arrangement (C1-C3) is halved and that halved voltage is compared with said reference voltage (V R ) to provide the next significant bit output of the converter.
Claim 19
Dependent Claim
288 words
An echo canceller (1) for enabling full duplex digital data communication in a transmitter/receiver unit when connected via a hybrid (2) circuit to one end of a two-wire line (3), in which a compensation unit (4) is addressed by a sequence of data bits transmitted over a predetermined data interval, in which the compensation unit (4) contains information from which is each of a number of sample periods per data bit period there is provided a digital estimate of the near end echo of the data transmitted over said data interval, in which each said digital estimate is applied via a digital-to-analogue converter (7) to an analogue summation circuit (8) together with the received signal to suppress said near end echo in the received signal, and in which an error signal circuit (9) derives from the output of the analogue summation circuit an error signal which is applied to the compensation unit (4) such that once per sample period the information in the compensation unit is adjusted, characterised in that the error signal circuit (9) is an analogue-to-digital converter which converts a sampled output of the analogue summation circuit to an exponentially quantised digital error signal, and in that in the analogue-to-digital converter the sampled output (SH) of the analogue summation circuit (8) is applied as an input voltage to charge a capacitor arrangement (C1-C3) to an initial voltage which is compared with a reference voltage (V R ) to provide at least significant bit output of the converter, after which in each of successive steps the voltage on the capacitor arrangement (C1-C3) is halved and that halved voltage is compared with said reference voltage (V R ) to provide the next significant bit output of the converter.
Claim 20
Dependent Claim
85 words
An echo canceller as claimed in Claim 17, in which the compensation unit is a memory unit (41) which contains a set of digital estimates of said near end echo, each digital estimate of the set corresponding to one of said number of sampled periods and one of the possible said sequences of data bits, and in which the error signal is applied to the memory unit (4) such that once per sample period an error adjusted digital estimate is written into the memory unit.
Claim 21
Dependent Claim
138 words
An echo canceller as claimed in Claim 17, in which the compensation unit is a memory unit (4) having memory partitions (41-44) each of which is addressed by a sequence of data bits transmitted over part of said data interval, in which once per sample period there is directly read from each memory partition (41-44) a digital estimate of the near end echo of the data transmitted over a corresponding part of said data interval, in which the memory unit said digital estimates read at the same time are added(61-63) to provide said digital estimate of the near end echo of the data transmitted over said data interval, and in which the error signal is applied to the memory unit such that once per sample period an error adjusted digital estimate is written into each memory partition (41-44).
Claim 22
Dependent Claim
138 words
An echo canceller as claimed in any one of Claims 17 to 19, in which the analogue-to-digital converter (9) includes a single comparator (COMP) and a switching arrangement (SW1-SW3) by means of which said input voltage is first applied to the comparator (COMP) to determine the sign of that input voltage and to provide an output bit of the converter indicative of that sign, said reference voltage (V R ) and said initial voltage on the capacitor arrangement (C1-C3) then being applied in dependence on said determined sign of the input voltage to appropriate inputs of the comparator (COMP) to prvide said least significant and succeeding output bits of the converter, and in which said sign bit and said least significant and succeeding bits are combined to provide the result of analogue-to-digital conversion in a predetermined bipolar code.
References Cited (Backward Citations)
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