High resolution graphics machine architecture

Claim 2

A graphics and image display system comprising: a plurality of drawing processors a pipeline processor, connected to said plurality of drawing processors, for broadcasting to said drawing processors, and an output controller for interfacing output signals from said processing elements with a display device.

Claim 3

The system of claim 1 wherein said drawing processors form a parallel arrangement of processors, where each of the processors is responsive to said pipeline processor.

Claim 4

The system of claim 1 wherein said drawing processors are interconnected to permit communication between said drawing processors.

Claim 5

The system of claim 1 wherein said pipeline processor comprises a plurality of transformation processors.

Claim 6

The system of claim 3 wherein said plurality of transformation processors are serially connected.

Claim 7

The system of claim 1 wherein said output controller includes control means for recieving output signals from a selected subset of said drawing processors.

Claim 8

The system of claim 5 wherein said control means alters selection of said subset in response to applied control signals.

Claim 9

The system of claim 1, further comprising a host processor for applying data to said pipeline processor.

Claim 10

The system of claim 1, further comprising a host processor for applying information to said pipeline processor, to said array of drawing processors, and to said output controller.

Claim 11

The system of claim 3 wherein each of said transformation processors comprises: an internal data bus; an input FIFO memory, responsive to applied signals, for delivering information to said internal bus; a digital signal processor connected between said internal bus and a program port; a memory connected to said internal bus; and an output FIFO memory interposed between said internal bus and an output port of said transformation processor.

Claim 12

The system of claim 1 wherein each of said drawing processors in said array comprises: an internal data bus; an input FIFO memory, responsive to applied signals, for delivering information to said internal bus; a digital signal processor connected between said internal bus and a program port; a memory connected to said internal bus; and an video memory interposed between said internal bus and an output port of said processing element.

Claim 13

A graphics and image display system comprising: an array of interconnected drawing processors; a pipeline processor for broadcasting to said processing elements; and an output controller for receiving output signals from a selected subset of said processing elements, where said selection is dynamically reconfigurable.

Claim 14

A graphics and image display system comprising: an array of interconnected drawing processors; a pipeline processor for broadcasting to said processing elements; and an output controller for receiving output signals from a selected subset of said processing elements, where said selection is dynamically reconfigurable.

Claim 15

In a system comprising K processor circuit boards, with each processor circuit board comprising m processors that develop signals on an output port at a rate M, and further comprising a video controller circuit board requiring the insertion of said signals at rate MPK, all of said circuit boards being connected to an interconnecting backplane that supports transmission of, at most, rate MP, CHARACTERIZED BY: multiplexing means situated in close proximity of said video controller board, having K input buses operating at rate MP and an output bus operating at rate MPK connected to said video controller; control means on each of said processors circuit boards for developing m enable signals that apply signals at an output port of each of said processors to an output bus of said processor circuit board; means for interconnecting groups of P circuit boards by multiplexing the output buses of the circuit boards in each group; and transmission means on said backplane for connecting the interconnected buses of each group to a different one of said input buses of said multiplexing means.

Claim 16

In a system comprising K processor circuit boards, with each processor circuit board comprising m processors that develop signals on an output port at a rate M, and further comprising a video controller circuit board requiring the insertion of said signals at rate MPK, all of said circuit boards being connected to an interconnecting backplane that supports transmission of, at most, rate MP, CHARACTERIZED BY: multiplexing means situated in close proximity of said video controller board, having K input buses operating at rate MP and an output bus operating at rate MPK connected to said video controller; control means on each of said processors circuit boards for developing m enable signals that apply signals at an output port of each of said processors to an output bus of said processor circuit board; means for interconnecting groups of P circuit boards by multiplexing the output buses of the circuit boards in each group; and transmission means on said backplane for connecting the interconnected buses of each group to a different one of said input buses of said multiplexing means.

Claim 17

The system of claim 12 wherein said control means is responsive to applied control signals that dictate the application of signals to said output port.