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EP0303193A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Toshiba Corp
•
Filing: 1988-08-04
•
Granted: —
•
Expires: 2008-08-04
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Abstract

Abstract A semiconductor integrated circuit device is pro­vided which comprises a first charge pumping circuit (1) comprising a plurality of MOS transistors (T1, T2, ..., Tn) cascade-connected between an input voltage node (IN1) and a booster output node (OUT1), where, of all associated nodes, those odd-numbered nodes receive one (φ1) of first and second clock signals (φ1, φ2) through a corresponding capacitor (C1) and those even-numbered nodes (N1, N3, ... Nn-2) receive the other clock signal (φ2) through a corresponding capacitor (C2), a second charge pumping circuit (2) comprising a plurality of MOS transistors (T1a, T2a, ..., Tna) cascade-connected bet­ween the input voltage node (IN1) and the booster output node (OUT2) and equal in number to those of the first charge pumping circuit (1) where, of all associated nodes, those odd-numbered nodes (N2a, N4a, ..., Nna-1) receive one (φ2) of first and second clock signals (φ1, φ2) through a corresponding capacitor (2) and those even-numbered nodes (N1a, N3a, ..., Nna-2) receive the other clock signal (φ1) through a corresponding capaci­tor (C4) and the gates of the respective MOS transistors (T1a, T2a, ..., Tna) are connected to the gate of the corresponding MOS transistors (T1, T2, ..., Tn), and a high resistive element (3) connectd to an output ter­minal of said first charge pumping circuit (1).

Inventors

  • 👤 Jun-Ichi Patent Division Tsujimoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-04 02:15
CPC Classifications
G; G11; G11C; G11C17/00; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 112 words
A semiconductor integrated circuit device equipped with an internal booster circuit, comprising: a first boost-up circuit (1) connected to a first input voltage node (IN1) to receive a power source voltage (V DD ); a second boost-up circuit (2) includes a plurality of MOS transistors (T1a ... Tna) whose gates receive a voltage boosted up by the first boost-up circuit (1) and adapted to compensate for a voltage drop resulting from a respective threshold voltage of the MOS transistors (T1a ... Tna); and a high resistive element connected to an output node (OUT1) of the first boost-up circuit to prevent a current loss from the first boost-up circuit (1) to an outside.
Claim 2
Dependent Claim 112 words
A semiconductor integrated circuit device equipped with an internal booster circuit, comprising: a first boost-up circuit (1) connected to a first input voltage node (IN1) to receive a power source voltage (V DD ); a second boost-up circuit (2) includes a plurality of MOS transistors (T1a ... Tna) whose gates receive a voltage boosted up by the first boost-up circuit (1) and adapted to compensate for a voltage drop resulting from a respective threshold voltage of the MOS transistors (T1a ... Tna); and a high resistive element connected to an output node (OUT1) of the first boost-up circuit to prevent a current loss from the first boost-up circuit (1) to an outside.
Claim 3
Dependent Claim 132 words
The semiconductor integrated circuit device according to claim 1, in which said first boost-up cir­cuit constitutes a first charge pumping circuit (1) comprising a plurality of MOS transistors (T1 ... Tn) connected in a cascaded fashion and connection nodes (N1 ... Nn-1) between the MOS transistor (T1) and the MOS transistor (Tn) serve as a plurality of boost-up stages and said second boost-up circuit constitutes a second charge pumping circuit constitutes a second charge pumping circuit (2) comprising a plurality of cascade-­connected MOS transistors (T1a ... Tna) equal in number to those of said first charge pumping circuit (1) and the respective gate of said MOS transistors (T1a ... Tn-1) receives a corresponding boost-up voltage from a corresponding one of said connection nodes (N1 ... Nn-1) of said first charge pumping circuit.
Claim 4
Dependent Claim 110 words
The semiconductor integrated circuit device according to claim 2, in which said boost-up circuit (1) constitutes an internal boost-up circuit comprising a plurality of MOS transistors (T1 ... Tn) cascade-connected between said first input node (IN1) and said high resistive element (3) with the gate of the MOS transistor connected to the drain of the same tran­sistor, in which, of nodes (N1 ... Nn-1) between the MOS transistor (T1) and the MOS transistor (Tn), those odd-­numbered nodes receive one of first and second signals of a different phase through a corresponding capacitor (C1 or C2) and those even-numbered nodes receive the other signal through a corresponding capacitor (C2 or C1).
Claim 5
Dependent Claim 135 words
The semiconductor integrated circuit device according to claim 2, in which said second boost-up circuit constitutes a charge pumping circuit (2) comprising said plurality of MOS transistors (T1 ... Tn) cascade-connected between a second input voltage node (IN2) and a second booster output node (OUT2) and equal in number to those of said first boost-up circuit, in which, of nodes (N1a ... Nna) provided between the MOS transistor (T1a) and the MOS transistor (Tna), those odd-numbered nodes receive one of first and second signals of a different phase through a corresponding capacitor (C1 or C2) and those even-numbered nodes receive the other signal through a corresponding capaci­tor (C2 or C1) and the respective gate of said MOS tran­sistors (T1a ... Tna) is connected to a corresponding boost-up stage of said first charge pumping circuit (1).

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