EP0302290A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Automatic frequency control system
Assignee: Motorola Solutions Inc
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Filing: 1988-07-18
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Granted: —
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Expires: 2008-07-18
Abstract
Abstract An automatic frequency control circuit (AFC) (10) is disclosed for use in a television receiver the latter of which includes a local oscillator (LO), an intermediate frequency (IF) demodulator section, and a phase locked loop (PLL) for acquiring and phase locking onto the IF signal. The AFC circuit comprises an acquisition circuit (72) for sensing and detecting a no signal condition, an out of lock signal condition and phase locked condition. During a no signal condition the acquisition circuit enables offset (76) and clamp (70) circuits for respectively setting the nominal operating frequencies of the voltage controlled oscillator (VCO) of the PLL and the LO to the center frequency of the IF passband. Upon appearance of an IF signal the acquisition circuit enables a sweep circuit (78) as the receiver is in an out of lock condition in order to sweep the VCO downward from the passband center frequency to just above the sound carrier frequency and then sweeps the VCO frequency upwards toward the video carrier frequency. During the downward sweep of the VCO the acquisition circuit disables the phase detector of the PLL to inhibit spurious lock up. Upon the VCO phase locking to the IF signal the clamp, sweep and offset circuits are disabled while the phase detector is enabled.
Inventors
- 👤 Michael Mcginn
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 14:27
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/083; H03H; H03H11/00; H03H11/02; H03H11/16; H03H11/20; H03J; H03J7/00; H03J7/02; H03J7/04; H03J7/047; H03J7/06; H03J7/065; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/12; H04; H04N; H04N5/00; H04N5/44; H04N5/455; H04N5/50
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
218 words
An automatic frequency control circuit (10) for use in a television receiver having a local oscillator (LO)(64), demodulator section including a pair of quadrature operated demodulators (38, 54), a phase locked loop (20) including a phase detector (18 and a voltage controlled oscillator (VCO) for phase locking onto a received IF signal, said automatic frequency control circuit being characterized by: sensing circuit (72) for detecting the absence or presence of the IF signal to provide a plurality of enabling and disabling control signals at respective outputs, said sensing circuit being coupled to respective outputs of the demodulators; an offset circuit (76) coupled to a first output of said sensing circuit which is enabled there in the absence of the IF signal for providing a control signal to the VCO causing the nominal operating frequency thereof to change to a first predetermined frequency; a clamp circuit (70) coupled to a second output of said sensing circuit which is enabled there in the absence of the IF signal for providing a control signal to the LO thereby causing the nominal operating frequency thereof to be changed to a second predetermined frequency; and said sensing circuit (72) disabling said offset circuit and said clamp circuit in the presence of the IF signal and the phase locked loop becoming phase locked thereto.
Claim 2
Dependent Claim
218 words
An automatic frequency control circuit (10) for use in a television receiver having a local oscillator (LO)(64), demodulator section including a pair of quadrature operated demodulators (38, 54), a phase locked loop (20) including a phase detector (18 and a voltage controlled oscillator (VCO) for phase locking onto a received IF signal, said automatic frequency control circuit being characterized by: sensing circuit (72) for detecting the absence or presence of the IF signal to provide a plurality of enabling and disabling control signals at respective outputs, said sensing circuit being coupled to respective outputs of the demodulators; an offset circuit (76) coupled to a first output of said sensing circuit which is enabled there in the absence of the IF signal for providing a control signal to the VCO causing the nominal operating frequency thereof to change to a first predetermined frequency; a clamp circuit (70) coupled to a second output of said sensing circuit which is enabled there in the absence of the IF signal for providing a control signal to the LO thereby causing the nominal operating frequency thereof to be changed to a second predetermined frequency; and said sensing circuit (72) disabling said offset circuit and said clamp circuit in the presence of the IF signal and the phase locked loop becoming phase locked thereto.
Claim 3
Dependent Claim
124 words
The automatic frequency control circuit of claim 1 including: said sensing circuit (72) being responsive to the presence of an IF signal while the phase locked loop is in an out of lock condition for providing an additional enabling signal; a sweep circuit (78) responsive to said additional enabling signal applied thereto from said sensing circuit for providing a sweep control signal 1 the VCO which causes the frequency of the VCO to sweep first downward from said first predetermined frequency to a third predetermined frequency and then to sweep upward towards the nominal operating frequency; and said sensing circuit being responsive to said VCO becoming phased locked to the IF signal for disabling said offset circuit, said sweep circuit and said clamp circuit.
Claim 4
Dependent Claim
38 words
The automatic frequency control circuit of claim 2 wherein said sensing circuit (72) provides a disable signal to the phase detector (18) during the time that the VCO is being swept downward in frequency by said sweep circuit.
Claim 5
Dependent Claim
143 words
A television receiver circuit including the automatic frequency control circuit of claim 1, 2 or 3 and a demodulator section comprising: first (14) and second (16) cascoded limiter stages for limiting the amplitude of an input signal applied to said first limiter stage; the phase locked loop (PLL) (20) coupled to the output of said second limiter stage for providing an output signal at outputs thereof representative of the input signal, said PLL including the voltage controlled oscillator (VCO) (24) operated at half the frequency of the input signal, and third (30) and fourth (32) cascoded limiter stages; a phase shift circuit (34) receiving the input signal for providing a predetermined amount of phase shift thereto; and the demodulator circuit (36) receiving both said phase shifted input signal and said representative signal for demodulating the input signal to provide a detected output signal.
Claim 6
Dependent Claim
32 words
The television receiver circuit of claim 4 including a direct current (dc) feedback circuit (40) coupled between the output of said second limiter stage and the input of said first limiter stage.
Claim 7
Dependent Claim
97 words
The television circuit of claim 5 wherein said PLL includes: phase detector circuit (18) coupled to said output of said second limiter stage and the output of said fourth limiter stage for providing an error signal whenever the limited input signal is other than in phase quadrature to the VCO signal; a low pass filter (22) coupled between said phase detector means and said VCO; and multiplier circuit (28) coupled between the output of said VCO and the input of said third limiter stage for doubling the frequency of said VCO signal to provide said representative signal.
Claim 8
Dependent Claim
85 words
The television receiver of claim 5 wherein said dc feedback circuit includes: first (42) and second (44) resistors series coupled between a first output of said second limiter stage and a first input of said first limiter stage; third (46) and fourth (148) series coupled resistors coupled between a second output of said second limiter stage and a second input of said first limiter stage; and a capacitor (50) coupled between the interconnections of said first and second resistors and said third and fourth resistors.
Claim 9
Dependent Claim
149 words
A phase shift circuit (34), comprising: a first differential amplifier including first (164) and second (172) transistors, the base of said second transistor being biased at a reference potential; a second differential amplifier including third (166) and fourth (178) transistors, the base of said fourth transistor being biased at said reference potential, the bases of said first and third transistors being coupled to a pair of inputs of the phase shift circuit to which a differential input voltage is supplied; a first capacitor (174) coupled between the emitters of said first and second transistors; a second capacitor (176) coupled between the emitters of said third and fourth transistors; a first resistor (188) coupled between said emitters of said second and fourth transistors; a second resistor (186) coupled between said emitters of said first and third transistors; and the collectors of said second and fourth transistors to a load (184).
Claim 10
Dependent Claim
149 words
A phase shift circuit (34), comprising: a first differential amplifier including first (164) and second (172) transistors, the base of said second transistor being biased at a reference potential; a second differential amplifier including third (166) and fourth (178) transistors, the base of said fourth transistor being biased at said reference potential, the bases of said first and third transistors being coupled to a pair of inputs of the phase shift circuit to which a differential input voltage is supplied; a first capacitor (174) coupled between the emitters of said first and second transistors; a second capacitor (176) coupled between the emitters of said third and fourth transistors; a first resistor (188) coupled between said emitters of said second and fourth transistors; a second resistor (186) coupled between said emitters of said first and third transistors; and the collectors of said second and fourth transistors to a load (184).
Claim 11
Dependent Claim
24 words
A televison receiver circuit of claim 4, 5, 6 or 7 wherein the phase shift circuit comprises the phase shift circuit of claim 8.
References Cited (Backward Citations)
No citation records indexed.
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