EP0301501A2 — Fault tolerant digital data processor with improv…

Claim 1

Independent Claim 138 words

In a method for operating a digital data processor having an input/output controller for communicating with one or more peripheral devices connected along a common peripheral device bus, wherein each said peripheral device can include device interface means for transferring information signals between the associated peripheral device and the peripheral bus means, the improvement comprising the steps of A. providing first and second input/output buses each for carrying data, address, control, and timing information between said input/output controller and said one or more peripheral devices, B. transmitting on said first and second input/output buses duplicative, synchronous and simultaneous strobe signals, said strobe signals defining successive timing intervals for information transfers along said first and second input/output buses, and C. transferring, in the absence of selected fault, information synchronously, simultaneously and duplicatively on said first and second input/output buses.

Claim 2

Dependent Claim 138 words

In a method for operating a digital data processor having an input/output controller for communicating with one or more peripheral devices connected along a common peripheral device bus, wherein each said peripheral device can include device interface means for transferring information signals between the associated peripheral device and the peripheral bus means, the improvement comprising the steps of A. providing first and second input/output buses each for carrying data, address, control, and timing information between said input/output controller and said one or more peripheral devices, B. transmitting on said first and second input/output buses duplicative, synchronous and simultaneous strobe signals, said strobe signals defining successive timing intervals for information transfers along said first and second input/output buses, and C. transferring, in the absence of selected fault, information synchronously, simultaneously and duplicatively on said first and second input/output buses.

Claim 3

Dependent Claim 112 words

In a method according to claim 1, the further improvement comprising the step of executing at least one step selected from the steps of. A. a scanner cycle step for determining an operational state of at least one said peripheral device connected to said common peripheral bus, B. a command cycle step for controlling operation of at least one said peripheral device connected to said common peripheral bus, C. a read cycle step for effecting the transfer of data signals from the peripheral device to the input/output controller, and D. a write cycle step for effecting the transfer of data signals from the input/output controller to at least one said peripheral device.

Claim 4

Dependent Claim 97 words

In a method according to claim 2, the further improvement wherein each of said scanner cycle, command cycle, read cycle, and write cycle steps comprising the steps of A. transmitting, during a first timing interval, duplicatively and synchronously on said first and second input/output buses a first status signal indicative of cycle initiation, and B. transmitting, in the absence of error and during said first timing interval, duplicatively and synchronously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle.

Claim 5

Dependent Claim 136 words

In a method according to claim 3, the further improvement wherein each of said scanner cycle, command cycle, read cycle, and write cycle steps comprises the step of receiving, in absence of error and during a second said timing interval, duplicatively and synchronously on said first and second input/output buses, a third status signal indicative of an operational state of a peripheral device addressed in said first timing interval, said second timing interval being subsequent to said first timing interval, said third status signal including at least one of i) a signal indicative of an operational state of the addressed peripheral device, ii) a signal indicative of an request associated with the addressed peripheral device, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

Claim 6

Dependent Claim 49 words

In a method according to claim 4, the further improvement wherein said command cycle step comprises the step of transmitting duplicatively and synchronously on said first and second input/output buses a command signal during a third timing interval, said third timing interval being subsequent to said second timing interval.

Claim 7

Dependent Claim 45 words

In a method according to claim 5, the further improvement wherein said write cycle step comprises the step of transmitting duplicatively and synchronously on said first and second input/output buses and during said third timing interval at least a portion of a data write address.

Claim 8

Dependent Claim 73 words

In a method according to claim 6, the further improvement wherein said write cycle step comprises the steps of A. transmitting synchronously and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, and B. transmitting synchronously and duplicatively on said first and second input/output buses a write signal during each timing interval in which write data is transmitted.

Claim 9

Dependent Claim 57 words

In a method according to claim 4, the further improvement wherein said read cycle step comprises the step of transmitting synchronously and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval, said read data address portion being transmitted in lieu of said command signal.

Claim 10

Dependent Claim 90 words

In a method according to claim 8, the further improvement wherein said read cycle step comprises the steps of A. receiving, in absence of error, synchronously and duplicatively on said first and second input/output buses read data from said peripheral device during one or more timing intervals subsequent to said third timing interval, and B. transmitting synchronously and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of data by the addressed peripheral device in a subsequent timing interval.

Claim 11

Dependent Claim 201 words

In a method according to claim 9, wherein said second timing interval immediately follows said first timing interval, and said third timing interval immediately follows said second timing interval, the further improvement wherein A. said write cycle step comprises the additional step of transmitting synchronously and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, and initiating transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and wherein B. said read cycle step comprises the additional step of transmitting synchronously and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, and initiating transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and said seventh following sixth.

Claim 12

Dependent Claim 110 words

In method according to claim 8, wherein each of said first and second input/output buses includes a data signal conductor set and a control signal conductor set, the further improvement comprising the steps of A. transmitting said first status signal on said control signal conductor set and transmitting said second status signal on said data signal conductor set, B. receiving said STATUS signal on said data signal conductor set, C. transmitting said command signal on said data signal conductor set, and D. transmitting said write signals and said read signals on said control signal set and transmitting said write data and receiving read data on said data signal conductor set.

Claim 13

Dependent Claim 40 words

In a method according to claim 1, the further improvement comprising the step of responding to assertion of a wait signal received on at least one of said first and second input/output buses for delaying generation of said strobe signal.

Claim 14

Dependent Claim 44 words

In a method according to claim 12, the further improvement comprising the step of responding to assertion of said wait signal for a time period greater than a designated time period for entering an operational state for identifying a source of bus transmission error.

Claim 15

Dependent Claim 36 words

In a method according to claim 13, the further improvement comprising the step of transmitting synchronously, simultaneously and duplicatively on said first and second input/output buses during a designated error-handling time interval an error-checking data signal.

Claim 16

Dependent Claim 103 words

In a method for operating a digital data processor having an input/output controller for transferring information with one or more peripheral devices connected along a common peripheral device bus, the improvement comprising the steps of A. providing first and second input/output buses each for transmitting data, address, control, and timing information between said input/output controller and said one or more peripheral devices, B. transmitting on said first and second input/output buses duplicative, synchronous, and simultaneous strobe signals, each defining successive timing intervals, and C. executing information transfer cycles for normally transferring information synchronously, simultaneously and duplicatively on said first and second input/output buses.

Claim 17

Dependent Claim 103 words

In a method for operating a digital data processor having an input/output controller for transferring information with one or more peripheral devices connected along a common peripheral device bus, the improvement comprising the steps of A. providing first and second input/output buses each for transmitting data, address, control, and timing information between said input/output controller and said one or more peripheral devices, B. transmitting on said first and second input/output buses duplicative, synchronous, and simultaneous strobe signals, each defining successive timing intervals, and C. executing information transfer cycles for normally transferring information synchronously, simultaneously and duplicatively on said first and second input/output buses.

Claim 18

Dependent Claim 110 words

In a method according to claim 15, the further improvement wherein said information cycle executing step comprises at least one step selected from the steps of A. an adaptor scanner cycle step for effecting the transfer of a signal representative of an operational state of a selected peripheral device connected, B. an adaptor command cycle step for accepting peripheral device control information from the first and second input/output buses, C. an adaptor read cycle step for effecting the transmission data from the associated peripheral device to the first and second input/output buses, and D. an adaptor write cycle step for accepting write data from the first and second input/output buses.

Claim 19

Dependent Claim 95 words

The method according to claim 15 wherein each of said adaptor scanner, command, read, and write cycle steps comprise the steps of A. receiving, in absence of error, during a first timing interval duplicatively, synchronously, and simultaneously on said first and second input/output buses a first status signal indicative of cycle initiation, B. receiving, during said first timing interval and in absence of fault, duplicatively, synchronously, and simultaneously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle.

Claim 20

Dependent Claim 107 words

In a method according to claim 17, the further improvement wherein each of said adaptor scanner, command, read, and write cycle steps comprises the step of transmitting during a second said timing interval, duplicatively, synchronously and simultaneously on said first and second input/output buses, a third status signal indicative of an operational status of the associated peripheral device, said third status signal including at least one of i) a signal indicative of operational activity of said peripheral device, ii) a signal indicative of a pending interrupt, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

Claim 21

Dependent Claim 44 words

In a method according to claim 18, the further improvement wherein said adaptor command cycle step comprises the step of receiving, in absence of error, duplicatively, simultaneously, and synchronously on said first and second input/output buses a command signal during a third timing interval.

Claim 22

Dependent Claim 57 words

In a method according to claim 19, the further improvement wherein said adaptor write cycle step comprises the step of receiving, in absence of error, duplicatively, synchronously, and simultaneously on said first and second input/output buses at least a portion of a data write address, said data write address portion being received during said third timing interval.

Claim 23

Dependent Claim 83 words

In a method according to claim 20, the further improvement wherein said adaptor write cycle step comprises the steps of A. receiving, in absence of fault, synchronously, simultaneously, and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, B. receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses a write signal during each timing interval in which write data is received.

Claim 24

Dependent Claim 50 words

In a method according to claim 20, the further improvement wherein said adaptor read cycle step comprises the step of receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval.

Claim 25

Dependent Claim 94 words

In a method according to claim 21, the further improvement wherein said adaptor read cycle steps comprises the steps of A. transmitting, synchronously, simultaneously, and duplicatively on said first and second input/output buses read data from said peripheral device, said read data being transmitted during one or more timing intervals subsequent to said third timing interval, and B. receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of read data in a subsequent timing interval.

Claim 26

Dependent Claim 207 words

In a method according to claim 23, wherein said second timing interval immediately follows said first timing interval, said third timing interval immediately follows said second timing interval, the further improvement wherein A. said adaptor write cycle step comprises the steps of receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, initiating transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and wherein B. said adaptor read cycle step comprises the steps of receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, initiating transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and seventh following sixth.

Claim 27

Dependent Claim 119 words

In a method according to claim 22, wherein said first and second input/output buses each include a data signal conductor set and a control signal conductor set, the further improvement comprising the steps of A. receiving said first status signal on said control signal conductor set and includes means for receiving said second status signal on said data signal conductor set. B. transmitting said third status signal on said data signal conductor set, C. receiving said command signal on said data signal conductor set, and D. receiving said write signals and said read signals on said control signal set and further include means for respectively receiving said write data and transmitting read data on said data signal conductor set.

Claim 28

Dependent Claim 39 words

In a method according to claim 15, the further improvement comprising the step of generating a wait signal for at least temporarily delaying the continued transmission of information signals, including strobe signals, by said input/output controller along those buses.

Claim 29

Dependent Claim 44 words

In a method according to claim 15, the further improvement comprising the step of responding to selected fault for transmitting synchronously, simultaneously, and duplicatively on said first and second input/output buses at least one of an error-checking data signal and an error-checking control signal.

Claim 30

Dependent Claim 153 words

In a digital data processor operating according to the method of claim 1 and having a peripheral device controller for communicating with one or more peripheral devices connected along a common peripheral device bus, wherein each said peripheral device can include device interface means for transferring information signals between the associated peripheral device and the peripheral bus means, the improvement wherein A. said peripheral bus includes first and second input/output buses each for carrying data, address, control, and timing information, B. said peripheral device controller includes strobe means connected with said first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals, said strobe signals defining successive timing intervals for information transfers along said first and second input/output buses, and C. said peripheral device controller includes controller transfer cycle means for executing information transfer cycles for normally transferring information synchronously, simultaneously and duplicatively on said first and second input/output buses.

Claim 31

Dependent Claim 127 words

In a digital data processor according to claim 28, the further improvement wherein said controller transfer cycle means includes i. controller scanner cycle means for executing a scanner cycle to determine an operational state of at least one said peripheral device connected to said common peripheral bus, ii. controller command cycle means for executing a command cycle for controlling operation of at least one said peripheral device connected to said common peripheral bus, iii. controller read cycle means for executing a read cycle to effect the transfer of data signals from the peripheral device to the input/output controller, and iv. controller write cycle means for executing a write cycle to effect the transfer of data signals from the input/output controller to at least one said peripheral device.

Claim 32

Dependent Claim 115 words

In a digital data processor according to claim 28, the further improvement comprising controller cycle initiation means connected with said first and second input/output buses for initiating an information transfer cycle, said controller cycle initiation means including means for transmitting, during a first said timing interval, duplicatively and synchronously on said first and second input/output buses a first status signal indicative of cycle initiation, said controller cycle initiation means further including means for transmitting, in the absence of error and during said first timing interval, duplicatively and synchronously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle.

Claim 33

Dependent Claim 127 words

In a processor according to claim 30, the further improvement wherein said controller cycle initiation means includes means for receiving, in absence of error and during a second said timing interval, duplicatively and synchronously on said first and second input/output buses, a third status signal indicative of an operational state of a peripheral device addressed in said first timing interval, said second timing interval being subsequent to said first timing interval, said third status signal including at least one of i) a signal indicative of an operational state of the addressed peripheral device, ii) a signal indicative of an request associated with the addressed peripheral device, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

Claim 34

Dependent Claim 49 words

In a processor according to claim 31, the further improvement wherein said controller command cycle means includes means for transmitting duplicatively and synchronously on said first and second input/output buses a command signal during a third timing interval, said third timing interval being subsequent to said second timing interval.

Claim 35

Dependent Claim 58 words

In a processor according to claim 32, the further improvement wherein said controller write cycle means includes means for transmitting duplicatively and synchronously on said first and second input/output buses and during said third timing interval at least a portion of a data write address, said data write address portion being transmitted in lieu of said command signal.

Claim 36

Dependent Claim 80 words

In a processor according to claim 33, the further improvement wherein said controller write cycle means includes means for transmitting synchronously and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval, said controller write cycle means further including means for concurrently transmitting synchronously and duplicatively on said first and second input/output buses a write signal during each timing interval in which write data is transmitted.

Claim 37

Dependent Claim 57 words

In a processor according to claim 31, the further improvement wherein said controller read cycle means includes means for transmitting synchronously and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval, said read data address portion being transmitted in lieu of said command signal.

Claim 38

Dependent Claim 96 words

In a processor according to claim 35, the further improvement wherein said controller read cycle means includes means for receiving, in absence of error, synchronously and duplicatively on said first and second input/output buses read data from said peripheral device during one or more timing intervals subsequent to said third timing interval, said controller read cycle means further including means for transmitting synchronously and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of data by the addressed peripheral device in a subsequent timing interval.

Claim 39

Dependent Claim 212 words

In a processor according to claim 36, the further improvement wherein i) said second timing interval immediately follows said first timing interval, ii) said third timing interval, immediately follows said second timing interval, iii) said controller write cycle means includes means for transmitting synchronously and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, said write cycle means further including means for beginning transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and iv) said controller read cycle means includes means for transmitting synchronously and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, said read cycle means further including means for beginning transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and said seventh following sixth.

Claim 40

Dependent Claim 156 words

In a processor according to claim 35, the further improvement wherein each of said first and second input/output buses includes a data signal conductor set and a control signal conductor set, and wherein i) said controller cycle initiation means includes means for transmitting said first status signal on said control signal conductor set and includes means for transmitting said second status signal on said data signal conductor set, ii) said controller cycle initiation means further includes means for receiving said STATUS signal on said data signal conductor set, iii) said controller command cycle means includes means for transmitting said command signal on said data signal conductor set, and iv) said controller write cycle means and said read cycle means include means for respectively transmitting said write signals and said read signals on said control signal set and further include means for respectively transmitting said write data and receiving read data on said data signal conductor set.

Claim 41

Dependent Claim 44 words

In a processor according to claim 28, the further improvement wherein said strobe means includes strobe delay means responsive to assertion of a wait signal received on at least one of said first and second input/output buses for delaying generation of said strobe signal.

Claim 42

Dependent Claim 49 words

In a processor according to claim 39, the further improvement wherein said peripheral device controller includes error handling means responsive to assertion of said wait signal for a time period greater than a designated time period for entering an operational state for identifying a source of bus transmission error.

Claim 43

Dependent Claim 40 words

In a processor according to claim 40, the further improvement wherein said error handling means comprises means for transmitting synchronously, simultaneously and duplicatively on said first and second input/output buses during a designated error-handling time interval an error-checking data signal.

Claim 44

Dependent Claim 139 words

In a digital data processor operating according to the method of claim 15 and having peripheral device control means for transferring information with one or more peripheral devices connected along a common peripheral device bus, the improvement wherein A. said peripheral bus includes first and second input/output buses each for carrying data, address, control, and timing information, B. strobe means connected with each of said first and second input/output buses for transmitting thereon duplicative, synchronous, and simultaneous strobe signals, each defining successive timing intervals, and C. each said peripheral device includes an associated peripheral device adaptor providing an interface between the peripheral device and the peripheral device bus, and wherein said peripheral device adaptor includes adaptor transfer cycle means for executing information transfer cycles for normally transferring information synchronously, simultaneously and duplicatively on said first and second input/output buses.

Claim 45

Dependent Claim 116 words

In a digital data processor according to claim 42, the further improvement wherein said adaptor transfer cycle means includes i. adaptor scanner cycle means for executing an adaptor scanner cycle for effecting the transfer of a signal representative of an operational state of a selected peripheral device connected, ii. adaptor command cycle means for executing a adaptor command cycle to accept peripheral device control information from the first and second input/output buses, iii. adaptor read cycle means for executing an adaptor read cycle to effect the transmission data from the associated peripheral device to the first and second input/output buses, iv. adaptor write cycle means for accepting write data from the first and second input/output buses.

Claim 46

Dependent Claim 132 words

The processor according to claim 42 wherein each of said adaptor scanner cycle means, adaptor command cycle means, adaptor read cycle means, and adaptor write cycle means include adaptor cycle initiation means connected with said peripheral device bus for initiating an information transfer cycle, said adaptor cycle initiation means including means for receiving, in absence of error, during a first timing interval duplicatively, synchronously, and simultaneously on said first and second input/output buses a first status signal indicative of cycle initiation, said adaptor cycle initiation means further including means for receiving, during said first timing interval and in absence of fault, duplicatively, synchronously, and simultaneously on said first and second input/output buses, a second status signal indicative of at least one said peripheral device to be addressed during the information transfer cycle.

Claim 47

Dependent Claim 100 words

In a processor according to claim 44, the further improvement wherein said adaptor cycle initiation means includes means for transmitting during a second said timing interval, duplicatively, synchronously, and simultaneously on said first and second input/output buses, a third status signal indicative of an operational status of the associated peripheral device, said third status signal including at least one of i) a signal indicative of operational activity of said peripheral device, ii) a signal indicative of a pending interrupt, and iii) a bus status signal indicative of fault detected in at least one of said first and second input/output buses.

Claim 48

Dependent Claim 43 words

In a processor according to claim 45, the further improvement wherein said adaptor command cycle means includes means for receiving, in absence of error, duplicatively, simultaneously, and synchronously on said first and second input/output buses a command signal during a third timing interval.

Claim 49

Dependent Claim 63 words

In a processor according to claim 46, the further improvement wherein said adaptor write cycle means includes means for receiving, in absence of error, duplicatively, synchronously, and simultaneously on said first and second input/output buses at least a portion of a data write address, said data write address portion being received during said third timing interval and in lieu of said command signal.

Claim 50

Dependent Claim 90 words

In a processor according to claim 47, the further improvement wherein said adaptor write cycle means includes means for receiving, in absence of fault, synchronously, simultaneously, and duplicatively on said first and second input/output buses peripheral device write data during one or more timing intervals subsequent to said third timing interval. said adaptor write cycle means further including means for concurrently receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses a WRITE signal during each timing interval in which write data is received.

Claim 51

Dependent Claim 62 words

In a processor according to claim 47, the further improvement wherein said adaptor read cycle means includes means for receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses at least a portion of a data read address during said third timing interval, said data read address portion being received in lieu of said command signal.

Claim 52

Dependent Claim 99 words

In a processor according to claim 47, the further improvement wherein said adaptor read cycle means includes means for transmitting, synchronously, simultaneously, and duplicatively on said first and second input/output buses read data from said peripheral device, said read data being transmitted during one or more timing intervals subsequent to said third timing interval, said adaptor read cycle means further including means for receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses one or more read signals, each normally being associated with the transmission of read data in a subsequent timing interval.

Claim 53

Dependent Claim 223 words

In a processor according to claim 50, the further improvement wherein i) said second timing interval immediately follows said first timing interval, ii) said third timing interval immediately follows said second timing interval, iii) said adaptor write cycle means includes means for receiving, in absence of error, synchronously, simultaneously, and duplicatively on said first and second input/output buses remaining portions of said write data address during fourth and fifth timing intervals, said adaptor write cycle means further including means for beginning transmission of said one or more write data signals during a sixth timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and iv) said adaptor read cycle means includes means for receiving, in absence of error, synchronously, duplicatively, and simultaneously on said first and second input/output buses remaining portions of said read data address during fourth and fifth timing intervals, said adaptor read cycle means further including means for beginning transmission of said one or more read signals during a seventh timing interval, said fourth timing interval immediately following said third timing interval, said fifth timing interval immediately following said fourth timing interval, and said sixth timing interval immediately following said fifth timing interval, and seventh following sixth.

Claim 54

Dependent Claim 158 words

In a processor according to claim 49, the further improvement wherein each of said first and second input/output buses includes a data signal conductor set and a control signal conductor set, and wherein i) said adaptor cycle initiation means includes means for receiving said first status signal on said control signal conductor set and includes means for receiving said second status signal on said data signal conductor set, ii) said adaptor cycle initiation means further includes means for transmitting said third status signal on said data signal conductor set, iii) said adaptor command cycle means includes means for receiving said command signal on said data signal conductor set, and iv) said adaptor write cycle means and said adaptor read cycle means include means for respectively receiving said write signals and said READ signals on said control signal set and further include means for respectively receiving said write data and transmitting read data on said data signal conductor set.

Claim 55

Dependent Claim 39 words

In a processor according to claim 42, the further improvement comprising means for generating a wait signal for at least temporarily delaying the continued transmission of information signals, including strobe signals, by said peripheral device controller along those buses.

Claim 56

Dependent Claim 46 words

In a processor according to claim 42, the further improvement comprising fault detection means comprises means responsive to selected fault for transmitting synchronously, simultaneously, and duplicatively on said first and second input/output buses at least one of an error-checking data signal and an error-checking control signal.

Fault tolerant digital data processor with improved bus protocol

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