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EP0301460A2
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Ultraviolet erasable nonvolatile semiconductor device
Assignee: Toshiba Corp
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Filing: 1988-07-25
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Granted: —
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Expires: 2008-07-25
Abstract
Abstract An ultraviolet erasable nonvolatile semiconductor device has a floating gate (13), a control gate (18), and a gate insulating layer (17) interlayered between the floating gate and the control gate. The interlayered gate insulating layer (17) consists of three layers, a first silicon oxide layer (14), a silicon nitride layer (15) layered on the first silicon oxide layer, and a second silicon oxide layer (16). The second silicon oxide layer (16) as the top layer of the three-layered gate insulating layer (17) is 30 ANGSTROM or less in thickness.
Inventors
- 👤 Seiichi C/O Patent Division Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
93 words
In an ultraviolet erasable nonvolatile semiconductor device having a floating gate (13), a gate insulating layer (17) layered on the floating gate (13), and a control gate layered on the gate insulating layer (17), said gate insulating layer (17) consisting of a first silicon oxide layer (14), a silicon nitride layer (15) layered on the first silicon oxide layer (14), and a second silicon oxide layer (16) layered on the silicon nitride layer (15), the improvement characterized in that the thickness of said second silicon oxide layer (16) is 30 Å or less.
Claim 2
Dependent Claim
93 words
In an ultraviolet erasable nonvolatile semiconductor device having a floating gate (13), a gate insulating layer (17) layered on the floating gate (13), and a control gate layered on the gate insulating layer (17), said gate insulating layer (17) consisting of a first silicon oxide layer (14), a silicon nitride layer (15) layered on the first silicon oxide layer (14), and a second silicon oxide layer (16) layered on the silicon nitride layer (15), the improvement characterized in that the thickness of said second silicon oxide layer (16) is 30 Å or less.
Claim 3
Dependent Claim
24 words
The semiconductor device according to claim 1, characterized in that the thickness of said second silicon oxide layer (16) is 20 Å or less.
Claim 4
Dependent Claim
47 words
The semiconductor device according to claim 1, characterized in that when said first silicon oxide layer (14) and said silicon nitride layer (15) are set at 100 to 200 Å in thickness, said second silicon oxide layer (15) is set at 10 Å or more in thickness.
Claim 5
Dependent Claim
38 words
The semiconductor device according to claim 1, characterized in that said second silicon oxide layer (16) is formed by oxidizing the surface of said silicon nitride layer (15) as the ground for said second silicon oxide layer (16).
References Cited (Backward Citations)
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