Cache consistency protocol for multiprocessor system

Claim 2

A multiprocessor system comprising: a random access memory (RAM)(12); a plurality of central processing units (CPU's)(16); a plurality of cache memories (22), one of said cache memories being associated with each of said plurality of CPU's; a system bus (14) to which said RAM, said plurality of CPU'S, and said plurality of cache memories are coupled, said system bus enabling address and data information to be exchanged among said RAM, said plurality of CPU'S, and said plurality of cache memories; a first signal line (18) to which said plurality of cache memories are coupled; logic means (FIG. 2) associated with a first one of said cache memories, and coupled to said system bus, for determining whether said first cache memory is sharing data with a second one of said cache memories and, if so, generating a first signal level on said first signal line, and otherwise generating a second signal level on said first signal line; and logic means associated with said second cache memory, and coupled to said system bus, for enabling the processor associated with said second cache memory to write data through to said RAM if said first signal level is present on said first signal line, and for inhibiting said associated processor from writing data through to said RAM if said second signal level is present on said first signal line,

Claim 3

The multiprocessor system recited in claim 1 and further comprising: a second signal line (TCOMP) (20) to which said plurality of cache memories are coupled; and wherein said logic means associated with said first cache memory comprises means for generating a first signal level on said second signal line while said logic means is determining whether said first cache memory is sharing data with said second cache memory, and otherwise generating a second signal level on said second signal line; and wherein said logic means associated with said second cache memory comprises means for inhibiting the operation of the processor associated with said second cache memory if said first signal level is present on said second signal line, and for enabling said associated processor to complete its bus cycle if said second signal level is present on said second signal line.

Claim 4

The multiprocessor system recited in claim 1 and further comprising: a second signal line (20) to which said plurality of cache memories and said RAM are coupled; and wherein said logic means associated with said first cache memory comprises means for determining whether the data stored in said first cache memory is different from that stored in said RAM, and, if so, generating a first signal level on said second signal line, and otherwise generating a second signal level on said second signal line; and logic means associated with said RAM, and coupled to said second signal line, for inhibiting the operation of said RAM if said first signal level is present on said second signal line, and for enabling said RAM to operate if said second signal level is present on said second signal line.

Claim 5

The multiprocessor system recited in claim 1 and further comprising: a second signal line (20) to which said plurality of cache memories are coupled; and wherein said logic means associated with said first one of said cache memories comprises means for generating a first signal level on said second signal line when said first cache memory is performing a read access during a write-miss operation, and otherwise generating a second signal level on said second signal line; and wherein said logic means associated with said second cache memory comprises means for inhibiting the operation of the processor associated with said second cache memory if said first signal level is present on said second signal line, and for enabling said associated processor to complete its bus cycle if said second signal level is present on said second signal line.

Claim 6

A multi-processor system comprising: a random access memory (RAM) (12); a plurality of central processing units (CPU's) (16); a plurality of cache memories (22), one of said cache memories being associated with each of said plurality of CPU's; a system bus (14) to which said RAM, said plurality of CPU'S, and said plurality of cache memories are coupled, said system bus enabling address and data information to be exchanged among said RAM, said plurality of CPU'S, and said plurality of cache memories; a first signal line (18) to which said plurality of cache memories are coupled; logic means (FIG. 2) associated with a first one of said cache memories, and coupled to said system bus, for determining whether said first cache memory contains data having an address identical to that of data which is being read or written by a processor associated with a second one of said cache memories and, if so, generating a first signal level on said first signal line, and otherwise generating a second signal level on said first signal line; and logic means associated with said second cache memory, and coupled to said system bus, for enabling the processor associated with said second cache memory to write data through to said RAM if said first signal level is present on said first signal line, and for inhibiting said associated processor from writing data through to said RAM if said second signal level is present on said first signal line.

Claim 7

A multi-processor system comprising: a random access memory (RAM) (12); a plurality of central processing units (CPU's) (16); a plurality of cache memories (22), one of said cache memories being associated with each of said plurality of CPU's; a system bus (14) to which said RAM, said plurality of CPU'S, and said plurality of cache memories are coupled, said system bus enabling address and data information to be exchanged among said RAM, said plurality of CPU'S, and said plurality of cache memories; a first signal line (18) to which said plurality of cache memories are coupled; logic means (FIG. 2) associated with a first one of said cache memories, and coupled to said system bus, for determining whether said first cache memory contains data having an address identical to that of data which is being read or written by a processor associated with a second one of said cache memories and, if so, generating a first signal level on said first signal line, and otherwise generating a second signal level on said first signal line; and logic means associated with said second cache memory, and coupled to said system bus, for enabling the processor associated with said second cache memory to write data through to said RAM if said first signal level is present on said first signal line, and for inhibiting said associated processor from writing data through to said RAM if said second signal level is present on said first signal line.

Claim 8

The multiprocessor system recited in claim 5 and further comprising: a second signal line (20) to which said plurality of cache memories are coupled; and wherein said logic means associated with said first cache memory comprises means for generating a first signal level on said second signal line while said logic means is determining whether said first cache memory contains data having an address identical to that of data which is being read or written by said processor associated with said second cache memory, and otherwise generating a second signal level on said second signal line; and wherein said logic means associated with said second cache memory comprises means for inhibiting the operation of the processor associated with said second cache memory if said first signal level is present on said second signal line, and for enabling said associated processor to complete its bus cycle if said second signal level is present on said second signal line.

Claim 9

The multiprocessor system recited in claim 5 and further comprising: a second signal line (20) to which said plurality of cache memories and said RAM are coupled; and wherein said logic means associated with said first cache memory comprises means for determining whether the data stored in said first cache memory is different from that stored in said RAM, and, if so, generating a first signal level on said second signal line, and otherwise generating a second signal level on said second signal line; and logic means associated with said RAM, and coupled to said second signal line, for inhibiting the operation of said RAM if said first signal level is present on said second signal line, and for enabling said RAM to operate if said second signal level is present on said second signal line.

Claim 10

The multiprocessor system recited in claim 5 and further comprising: a second signal line (20) to which said plurality of cache memories are coupled; and wherein said logic means associated with said first one of said cache memories comprises means for generating a first signal level on said second signal line when said first cache memory is performing a read access during a write-miss operation, and otherwise generating a second signal level on said second signal line; and wherein said logic means associated with said second cache memory comprises means for inhibiting the operation of the processor associated with said second cache memory if said first signal level is present on said second signal line, and for enabling ssaid associated processor to complete its bus cycle if said second signal level is present on said second signal line.

Claim 11

In a data processing system comprising a system bus (14), a random access memory (RAM) (12) coupled to said system bus and storing information, a plurality of processors (16) coupled to said system bus and requiring read/write access to said information in said RAM over said system bus, and a plurality of cache memories (22) each associated with a representative one of said processors, a method of reducing accesses to said RAM over said system bus by said plurality of processors, said method comprising the steps of: determining, with respect to one of said cache memories, whether information stored therein is shared by one of said processors not associated with said one cache memory; and enabling said one processor to write said information to said RAM if said information stored in said one cache memory is shared, otherwise inhibiting said one processor from writing said information to said RAM.

Claim 12

In a data processing system comprising a system bus (14), a random access memory (RAM) (12) coupled to said system bus and storing information, a plurality of processors (16) coupled to said system bus and requiring read/write access to said information in said RAM over said system bus, and a plurality of cache memories (22) each associated with a representative one of said processors, a method of reducing accesses to said RAM over said system bus by said plurality of processors, said method comprising the steps of: determining, with respect to one of said cache memories, whether information stored therein is shared by one of said processors not associated with said one cache memory; and enabling said one processor to write said information to said RAM if said information stored in said one cache memory is shared, otherwise inhibiting said one processor from writing said information to said RAM.

Claim 13

In a data processing system comprising a system bus (14), a random access memory (RAM) (12) coupled to said system bus and storing information, a plurality of processors (16) coupled to said system bus and requiring read/write access to said information in said RAM over said system bus, and a plurality of cache memories (22) each associated with a respective one of said processors, a method of reducing accesses to said RAM over said system bus by said plurality of processors, said method comprising the steps of: determining, with respect to one of said cache memories, whether information stored therein is shared by a different one of said cache memories; and enabling the processor associated with said different cache memory to write said information to said RAM if said information stored in said one cache memory is shared, otherwise inhibiting said processor from writing said information to said RAM.

Claim 14

In a data processing system comprising a system bus (14), a random access memory (RAM) (12) coupled to said system bus and storing information, a plurality of processors (16) coupled to said system bus and requiring read/write access to said information in said RAM over said system bus, and a plurality of cache memories (22) each associated with a respective one of said processors, a method of reducing accesses to said RAM over said system bus by said plurality of processors, said method comprising the steps of: determining, with respect to one of said cache memories, whether information stored therein is shared by a different one of said cache memories; and enabling the processor associated with said different cache memory to write said information to said RAM if said information stored in said one cache memory is shared, otherwise inhibiting said processor from writing said information to said RAM.