EP0301277A2
Expired / Lapsed
EP
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Bit-line isolated, CMOS sense amplifier
Assignee: Advanced Micro Devices Inc
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Filing: 1988-07-05
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Granted: —
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Expires: 2008-07-05
Abstract
Abstract A sense amplifier includes a pair of decoupling transistors (P4, P5) for isolating the sense nodes (X, Y) from the bit lines (B, B ) during the assertion of a sense signal, thereby eliminating the occurrence of current spikes and increasing its gain.
Inventors
- 👤 Donald M. Walters, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 05:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
297 words
A sense amplifier coupled to a pair of bit lines for sensing and amplifying a voltage differential between the pair of bit lines, comprising: a first N-channel transistor (N5) having a drain electrode connected to a first sense node (X), a gate electrode connected to a second sense node (Y), and a source electrode; a second N-channel transistor (N6) having a drain electrode connected to the second sense node (Y ), a gate electrode connected to the first sense node (X), and a source electrode connected to the source electrode of the first N-channel transistor (N5); a first P-channel transistor (P6) having a source electrode connected to a supply potential (VCC), a gate electrode connected to the second sense node (Y), and a drain electrode connected to the first sense node (X); a second P-channel transistor (P7) having a source electrode connected to the supply potential (VCC), a gate electrode connected to the first sense node (X), and a drain electrode connected to the second sense node (Y); a third N-channel transistor (N7) having a drain electrode connected to the source electrodes of the first and second N-channel transistors (N5, N6) a gate electrode connected to receive a sense signal, and a source electrode connected to a ground potential (VSS); a third P-channel transistor (P4) having a source electrode connected to a first bit line (B) of the pair of bit lines, a gate electrode connected to receive the sense signal, and a source electrode connected to the first sense node (X); and a fourth P-channel transistor (P5) having a source electrode connected to a second bit line ( B ) of the pair of bit lines, a gate electrode connected to receive the sense signal, and a source electrode connected to the second sense node (Y).
Claim 2
Dependent Claim
297 words
A sense amplifier coupled to a pair of bit lines for sensing and amplifying a voltage differential between the pair of bit lines, comprising: a first N-channel transistor (N5) having a drain electrode connected to a first sense node (X), a gate electrode connected to a second sense node (Y), and a source electrode; a second N-channel transistor (N6) having a drain electrode connected to the second sense node (Y ), a gate electrode connected to the first sense node (X), and a source electrode connected to the source electrode of the first N-channel transistor (N5); a first P-channel transistor (P6) having a source electrode connected to a supply potential (VCC), a gate electrode connected to the second sense node (Y), and a drain electrode connected to the first sense node (X); a second P-channel transistor (P7) having a source electrode connected to the supply potential (VCC), a gate electrode connected to the first sense node (X), and a drain electrode connected to the second sense node (Y); a third N-channel transistor (N7) having a drain electrode connected to the source electrodes of the first and second N-channel transistors (N5, N6) a gate electrode connected to receive a sense signal, and a source electrode connected to a ground potential (VSS); a third P-channel transistor (P4) having a source electrode connected to a first bit line (B) of the pair of bit lines, a gate electrode connected to receive the sense signal, and a source electrode connected to the first sense node (X); and a fourth P-channel transistor (P5) having a source electrode connected to a second bit line ( B ) of the pair of bit lines, a gate electrode connected to receive the sense signal, and a source electrode connected to the second sense node (Y).
Claim 3
Dependent Claim
58 words
A sense amplifier as claimed in Claim 1, wherein said third and fourth P-channel transistors (P4, P5) are turned off so as to isolate the pair of bit lines (B, B ) from the sense nodes (X, Y) when the sense signal is at a high logic level, thereby eliminating a current spike to the ground potential (VSS).
Claim 4
Dependent Claim
24 words
A sense amplifier as claimed in Claim 2, further comprising an equilibration circuit (12) connected between the pair of bit lines (B, B ).
Claim 5
Dependent Claim
23 words
A sense amplifier as claimed in Claim 3, wherein said equilibration circuit (12) comprises fifth, sixth and seventh P-channel transistors (P1, P3, P2).
Claim 6
Dependent Claim
106 words
A sense amplifier as claimed in Claim 4, wherein said fifth transistor (P1) has a source connected to the supply potential (VCC), a gate electrode connected to receive a precharge signal, and a drain electrode; said sixth transistor (P3) has a source electrode connected to the supply potential (VCC), a gate electrode connected to receive the precharge signal, and a drain electrode; and said seventh transistor (P2) has a first current electrode connected to the drain electrode of said fifth transistor (P1), a gate electrode connected to receive the precharge signal, and a second current electrode connected to the drain electrode of said sixth transistor (P3).
Claim 7
Dependent Claim
46 words
A sense amplifier as claimed in Claim 5, wherein said fifth, sixth and seventh transistors (P1, P3, P2) are turned on when the precharge signal is at a low logic level so as to equalize the voltage on the pair of bit lines (B, B )
Claim 8
Dependent Claim
289 words
A sense amplifier coupled to a pair of bit lines for sensing and amplifying a voltage differential between the pair of bit lines, comprising: a first N-channel transistor (N5) having a drain electrode connected to a first sense node (X), a gate electrode connected to a second sense node (Y), and a source electrode; a second N-channel transistor (N6) having a drain electrode connected to the second sense node (Y), a gate electrode connected to the first sense node (X ), and a source electrode connected to the source electrode of the first N-channel transistor (N5); a first P-channel transistor (P6) having a source electrode connected to a supply potential (VCC), a gate electrode connected to the second sense node (Y), and a drain electrode connected to the first sense node (X); a second P-channel transistor (P7) having a source electrode connected to the supply potential (VCC), a gate electrode connected to the first sense node (X), and a drain electrode connected to the second sense node (Y); a third N-channel transistor (N7) having a drain electrode connected to the source electrodes of the first and second N-channel transistors (N5, N6) a gate electrode connected to receive a sense signal, and a source electrode connected to a ground potential (VSS); first decoupling means responsive to said sense signal and being interconnected between said first bit line (B) and said first sense node (X) for eliminating a current spike when said sense signal is at a high logic level; and second decoupling means responsive to said sense signal and being interconnected between said second bit line ( B ) and said second sense node (Y) for eliminating a current spike when said sense signal is at a high logic level.
Claim 9
Dependent Claim
289 words
A sense amplifier coupled to a pair of bit lines for sensing and amplifying a voltage differential between the pair of bit lines, comprising: a first N-channel transistor (N5) having a drain electrode connected to a first sense node (X), a gate electrode connected to a second sense node (Y), and a source electrode; a second N-channel transistor (N6) having a drain electrode connected to the second sense node (Y), a gate electrode connected to the first sense node (X ), and a source electrode connected to the source electrode of the first N-channel transistor (N5); a first P-channel transistor (P6) having a source electrode connected to a supply potential (VCC), a gate electrode connected to the second sense node (Y), and a drain electrode connected to the first sense node (X); a second P-channel transistor (P7) having a source electrode connected to the supply potential (VCC), a gate electrode connected to the first sense node (X), and a drain electrode connected to the second sense node (Y); a third N-channel transistor (N7) having a drain electrode connected to the source electrodes of the first and second N-channel transistors (N5, N6) a gate electrode connected to receive a sense signal, and a source electrode connected to a ground potential (VSS); first decoupling means responsive to said sense signal and being interconnected between said first bit line (B) and said first sense node (X) for eliminating a current spike when said sense signal is at a high logic level; and second decoupling means responsive to said sense signal and being interconnected between said second bit line ( B ) and said second sense node (Y) for eliminating a current spike when said sense signal is at a high logic level.
Claim 10
Dependent Claim
19 words
A sense amplifier as claimed in Claim 7, wherein said first decoupling means comprises a third P-channel transistor (P4).
Claim 11
Dependent Claim
19 words
A sense amplifier as claimed in Claim 8, wherein said second decoupling means comprises a fourth P-channel transistor (P5).
References Cited (Backward Citations)
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