Emitter coupled logic circuit

Claim 2

An emitter coupled logic circuit comprising a plurality of transistors (Q1, Q2, Q3) constituting current switches for receiving input signals and outputting mutually opposite first and second outputs, emitters of the plurality of transistors being mutually connected; first emitter follower means (Q4) for extracting the first output, the extracted first output being outputted through a first output terminal; and second emitter follower means (Q5) for extracting the second output, the extracted second output being outputted through a second output terminal; characterized in that the emitter coupled logic circuit comprises variable impedance (20) means being connected to at least one of the first and second output terminals for variably providing an impedance to be coupled with said one output terminal, an impedance to be provided when both the levels of the extracted first and second outputs are at a high-level being smaller than an impedance to be provided when at least one of the first and second outputs is at a low-level.

Claim 3

An emitter coupled logic circuit as claimed in claim 1, characterized in that the variable impedance circuit comprises a first pair of transistors (Q11, Q12), emitters of which are connected to each other; a second pair of transistors (Q13, Q14), emitters of which are connected to each other, a collector of one (Q11) of the first paired transistors and a collector of one (Q13) of the second paired transistors being connected to each other, a collector of the other (Q12) of the first paired transistors and a collector of the other (Q14) of the second paired transistors being connected to each other and also to a positive power source (V CC ) through a resistor (R C ), a base of said one (Q11) of the first paired transistors being connected to the first output terminal of the first emitter follower means (Q4), a base of said one (Q13) of the second paired transistors being connected to the second output of the second emitter follower means (Q5), bases of said the others (Q12, Q14) of the first and second paired transistors being supplied with a reference voltage (V BB ); constant current source means being connected between the emitters of each of the first and second paired transistors and a negative power source (-V EE ); and third emitter follower means (Q15) being connected to the collectors of said the other (Q12, Q14) of the first and second paired transistors for controlling ON/OFF states of the constant current means (Q16).

Claim 4

An emitter coupled logic circuit as claimed in claim 2, characterized in that said the other transistors of the first and second paired transistors are constituted by one transistor (Q17) having two emitters.

Claim 5

An emitter coupled logic circuit as claimed in claim 2, characterized in that said constant current source means comprises two transistors (Q18, Q19), one of which is connected to the emitter of the first paired transistors (Q11, Q12), and the other of which is connected to the emitters of the second paired transistors (Q13, Q14), and in that bases of said two transistors are connected to the negative power source through a third register (R F ) and a diode (D₂), and are also connected to the third emitter follower means, and emitters of said two transistors are connected to the negative power source through respective emitter resistors (R E1 , R E2 ).

Claim 6

An emitter coupled logic circuit as claimed in claim 2, characterized in that said constant current source comprises one transistor (Q16) having two collectors, one of which is connected to the emitters of the first paired transistors (Q11, Q12), and the other of which is connected to the emitters of the second paired transistors (Q13, Q14), and in that a base of said one transistor of the constant current source is connected to the negative power source through a third resistor (R F ) and a diode (D₂) and also to the third emitter follower means (Q15), and an emitter of said one transistor having the two collectors is connected to the negative power source (-V EE ) through an emitter resistor (R E ).

Claim 7

An emitter coupled logic circuit as claimed in claim 2, characterized in that the third emitter follower means comprises a transistor (Q15), a base of which is connected to the collectors of said the others (Q12, Q14) of the first and second paired transistors, an emitter of which is connected to the constant current source through a level shift diode (D1), and a collector of which is connected to the positive power source (V CC ).

Claim 8

An emitter coupled logic circuit as claimed in claim 1, characterized in that the variable impedance means comprises a first pair of transistors (Q20, Q21), emitters of which are connected to each other, a collector and base of one (Q20) of the first paired transistors being connected to the first output of the first emitter follower means (Q4), a base of the other of the first paired transistors being supplied with a reference voltage (R REF ); a second pair of transistors (Q22, Q23), emitters of which are connected to each other, a collector of one of the second paired transistors being connected to the emitters of the first pair of the transistors (Q20, Q21), a collector of the other (Q23) of the second paired transistors being connected to a collector of the other (Q21) of the first paired transistors, a base of the other (Q23) of the second paired transistors being supplied with another reference voltage (V BB1 ); a level adjusting transistor (Q24) for adjusting a bias level to be applied to a base of said one (Q22) of the first paired transistors, the level adjusting transistor being controlled by the second emitter follower means (Q5); constant current source means (Q16) being connected to the mutually connected emitters of the second pair of transistors (Q22, Q23); a driving transistor (Q15) for controlling ON/OFF states of the constant current source means' (Q16); and a controlling means (Q25) for forming a current path between the first output terminal and the negative power source.

Claim 9

An emitter coupled logic circuit as claimed in claim 7, characterized in that the constant current source comprises a transistor (Q16), a collector of which is connected to the emitters of the second pair of the transistors (Q22, Q23), an emitter of which is connected to the negative power source through a resistor (R E ), a base of which is connected to a base of the controlling transistor (Q25), and in that a collector of the controlling transistor (Q25) is connected to the collector of said one (Q20) of the first pair of transistors, an emitter of the controlling transistor (Q25) is connected to the negative power source through an emitter resistor (R G ), the base of which is connected to the negative power source through a base resistor (R F ).

Claim 10

An emitter coupled logic circuit as claimed in claim 7, characterized in that the level adjusting transistor (Q24) is an emitter follower, and characterized in that an emitter of the emitter follower transistor is connected to the base terminal of said one (Q22) of the second paired transistors, a collector of which is connected to the positive power source (V CC ), and a base of which is connected to the output of the second emitter follower means.

Claim 11

An emitter coupled logic circuit as claimed in claim 7, characterized in that the third emitter follower means comprises a transistor (Q15), a base of which is connected to said one (Q20) of the first paired transistors, a collector of which is connected to the positive power source (V CC ), and a base of which is connected to the constant current source means (Q16) through a level shift diode (D1, D2) and also to a base of the controlling transistor (Q25).

Claim 12

An emitter coupled logic circuit as claimed in claim 1, characterized in that the variable impedance means (20) is provided at each of the first and second output terminals.