EP0299674A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improvements in or relating to frequency synthesisers
Assignee: Plessey Overseas Ltd
•
Filing: 1988-07-07
•
Granted: —
•
Expires: 2008-07-07
Abstract
Abstract A frequency synthesiser is provided including a programmable divider, a register for holding a divisor word, a reference source and a sample-and-hold phase detector, in which the register is maintained active during power-down and in which a sequence controller is provided for controlling the sequence of activations of the synthesiser on power up and supplies a substantially constant voltage, during power-down, to the output of the phase detector equivalent to the in-lock output of the detector.
Inventors
- 👤 Nicholas Paul Cowley
- 👤 Thomas David Stephen Mcclelland
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 20:00
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/199; H03L3/00; H03L7/08; H03L7/0802; H03L7/10; H03L7/104; H03L7/183; H03L7/193; H03L7/085; H03L7/087
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
112 words
A frequency synthesiser having a phase locked loop including a programmable divider to which the output of a local oscillator may be fed, a reference source and, at least, a sample-and-hold phase detector which, in operation, provides an output at a substantially constant voltage when phase loop lock is established, a register for holding a divisor for use in the programmable divider and a sequence controller for controlling the power up sequence after a stand by period, characterised in that the register is maintained active during a stand by period, and in that, during power-down the a means is arranged to apply the substantially constant voltage at the output of the detector.
Claim 2
Dependent Claim
112 words
A frequency synthesiser having a phase locked loop including a programmable divider to which the output of a local oscillator may be fed, a reference source and, at least, a sample-and-hold phase detector which, in operation, provides an output at a substantially constant voltage when phase loop lock is established, a register for holding a divisor for use in the programmable divider and a sequence controller for controlling the power up sequence after a stand by period, characterised in that the register is maintained active during a stand by period, and in that, during power-down the a means is arranged to apply the substantially constant voltage at the output of the detector.
Claim 3
Dependent Claim
33 words
A synthesiser is claimed in claim 1 wherein the sequence controller is arranged, on power up, to reset the count of the programmable divider in synchronism with the output of the reference source.
Claim 4
Dependent Claim
28 words
A synthesiser as claimed in claim 1 or 2 wherein the phase detector is enabled by the sequence controller in synchronism with the output of the programmable divider.
Claim 5
Dependent Claim
16 words
A frequency divider substantially as hereinbefore described with reference to and illustrated in the accompanying drawings.
Claim 6
Dependent Claim
16 words
A frequency divider substantially as hereinbefore described with reference to and illustrated in the accompanying drawings.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.