An instruction control mechanism for a computer system

Claim 2

A register renaming apparatus for a computing system having a main memory comprising address­able locations containing data and instructions, said instructions including a plurality of fields including an operation field specifying an operation to be performed and at least one register designation field, each such register designation field being indicative of two of n architected registers for receiving data according to the operation specified in said operation field, said computing system including m physical registers, where m > n, characterized by a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers, with the architected register designation in said register designation field being replaced by the physical register number in the corresponding location in said map table prior to the associated instruction being executed; a free list of the ones of said m physical registers which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; and a holding register queue which receives remapped physical register designations from said map table of certain ones of said physical registers which are being utilized by instructions presently being executed, with said holding register queue temporarily storing said certain one of said physical register designations prior to entering them in said free list of physical registers following the execution of their associated instructions.

Claim 3

The combination claimed in claim 1, characterized by a store queue which has a physical register designation stored therein of a store operation to a register designated in said map table, with the physical register designation being made available to said free list upon completion of the store.

Claim 4

The combination claimed in claim 2, characterized by means for checking that a physical register designation in said holding register queue is not also in said store queue before sending said physical register designation to said free list.

Claim 5

The combination claimed in claim 2, characterized by means for determining that a store operation is not issued prior to the data for the associated physical register designation having been produced.

Claim 6

A register renaming apparatus for two instruc­tions at a time for a coprocessor system having a main memory comprising addressable locations containing data and instructions, said instruc­tions including a plurality of fields including an operation field specifying an operation to be performed and at least two register designation fields, each such register designation field including a tag indicative of one of n architected registers for receiving data according to the operation specified in said operation field, said computing system including m physical registers, where m > n, comprising a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers, with the architected register tag in said register designation field being replaced by a physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said m physical registers which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table as set forth in claim 1, characterized by a pending target return queue which receives remapped physical register tags from said map table of certain ones of said physical registers which are being utilized by instructions presently being executed, with said pending target return queue temporarily storing said certain ones of said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions.

Claim 7

The combination claimed in claim 5, characterized by a store queue which has a physical register tag stored therein of a floating point store operation to a register designated in said map table, with the physical register tag being made available to said free list upon completion of the store.

Claim 8

The combination claimed in claim 6, characterized by means for checking that a physical register tag in said pending target return queue is not also in said store queue before sending said physical register tag to said free list.

Claim 9

The combination claimed in claim 6, characterized by means for determining that a floating point store operation is not issued prior to the data for the physical register tag having been produced.

Claim 10

In a central processor-coprocessor system, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instruc­tions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designation fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory; a register file comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said control unit; a floating point arithmetic unit for receiving data from said register file and said main memory in accordance with said instructions and receiving control information from said control unit; register renaming means for receiving the architected register tags of instructions from said control unit, and providing physical register tags in place of said architected register tags to said control unit, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; and a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions.

Claim 11

In a central processor-coprocessor system, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instruc­tions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designation fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory; a register file comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said control unit; a floating point arithmetic unit for receiving data from said register file and said main memory in accordance with said instructions and receiving control information from said control unit; register renaming means for receiving the architected register tags of instructions from said control unit, and providing physical register tags in place of said architected register tags to said control unit, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; and a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions.

Claim 12

The combination claimed in claim 9, characterized by a store queue which has a physical register tag stored therein of a store to a register desig­nated in said map table, with the physical register tag being made available to said free list upon completion of the store

Claim 13

The combination claimed in claim 10, characterized by means for checking that a physical register tag in said pending target return queue is not also in said store queue before sending said physical register tag to said free list.

Claim 14

The combination claimed in claim 10, characterized by means for determining that a floating point store operation is not issued prior to the data for the physical register tag having been produced.

Claim 15

In a central processor-coprocessor system as set forth in claim 9, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instruc­tions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designa­tion fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which processes said load and store operations, and provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor which processes said floating point arithmetic operations, comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory, said control unit characterized by a synchronization unit which receives said synchronization signal from said central processor unit, and separates the operation code field from the architected register tags in each instruction; an instruction decode buffer which receives the operation code field from said synchronization unit and physical register tags from a register renaming means for each instruction; and a decoder for receiving instructions from said instruction decode buffer and decoding them for provision to a register file and arithmetic unit; a register file comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said decoder; a floating point arithmetic unit for receiving data from said register file and said main memory in accordance with said instructions and receiving control information from said decoder; register renaming means for receiving the architected register tags of instructions from said synchronization unit, and providing physical register tags in place of said architected register tags to said instruction decode buffer, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; and a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions.

Claim 16

The combination claimed in claim 13, characterized by a store queue which has a physical register tag stored therein of a store to a register desig­nated in said map table, with the physical register tag being made available to said free list upon completion of the store.

Claim 17

The combination claimed in claim 14, characterized by means for checking that a physical register tag in said pending target return queue is not also in said store queue before sending said physical register tag to said free list.

Claim 18

The combination claimed in claim 14, characterized by means for determining that a floating point store operation is not issued prior to the data for the physical register tag having been produced

Claim 21

The method of claim 17, characterized by further steps of: maintaining a store queue which has a physical register tag stored therein of a floating point store operation to a register designated in said map table, with the physical register tag being made available to said free list upon completion of the store.

Claim 22

The method of claim 18, characterized by further steps of: checking that a physical register tag in said pending target return queue is not also in said store queue before sending said physical register tag to said free list.

Claim 23

The method of claim 18, characterized by further steps of: determining that a floating point store operation is not issued prior to the data for the physical register tag having been produced.