EP0296718A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A coplanar and self-aligned contact structure
Assignee: HP Inc
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Filing: 1988-05-26
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Granted: —
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Expires: 2008-05-26
Abstract
Abstract An integrated circuit chip and a method of forming said chip. A substrate having a planar surface has formed thereon at least two field oxide regions (26, 27, 28) separated from each other, each having separate diffusion regions (31, 32), all coplanar with the planar surface. Over that are at least three separate coplanar polysilicon deposits (36, 37, 38), comprising a gate deposit (37) bridging over and between the two separate diffusion regions (31, 32), and second and third deposits (36, 38), each over one of two field oxide regions (26, 27). A highly conductive path (46, 47, 48) is formed over each polysilicon deposit, one (47) over the gate and confined thereto, and two others (46, 48), each extending from a top of a polysilicon deposit (36, 38) down to and in good electrical contact with its adjacent diffusion region (31, 32). A passivation layer (61, 62) overlies all of the integrated circuit portions so far described, covering all three of the polysilicon deposits, all of which are coplanar with each other. The passivation layer has an opening (63, 64) leading to each of the second (36) and third (38) coplanar polysilicon deposits. Metal contacts (66, 67) extend down into each said opening and to the polysilicon deport thereof.
Inventors
- 👤 Kuang-Yi Chiu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:02
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0186; H10D84/02; H10D84/03; H10D84/038; H10W20/064; H10W20/069; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441; H10D30/0212
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
209 words
A method of forming an integrated circuit chip comprising the steps of: (a) forming a substrate having a planar surface, (b) forming on said substrate at least two field oxide regions separated from each other and having two separated diffusion regions, namely a source diffusion region and a drain diffusion region, all coplanar with said planar surface, (c) forming at least three separate coplanar polysilicon deposits, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, (d) forming a highly conductive path over each said polysilicon deposit, the one over said gate being confined thereto, and the others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, (e) forming a passivation layer over all of said integrated circuit portions so far described, covering all three of the polysilicon deposits, all of which are coplanar with each other, (f) forming a hole in said passivation layer to each of said second and third coplanar polysilicon deposits, the holes being of identical depth, and (g) providing metal plug contacts extending into each said hole that are identical in height.
Claim 2
Independent Claim
209 words
A method of forming an integrated circuit chip comprising the steps of: (a) forming a substrate having a planar surface, (b) forming on said substrate at least two field oxide regions separated from each other and having two separated diffusion regions, namely a source diffusion region and a drain diffusion region, all coplanar with said planar surface, (c) forming at least three separate coplanar polysilicon deposits, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, (d) forming a highly conductive path over each said polysilicon deposit, the one over said gate being confined thereto, and the others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, (e) forming a passivation layer over all of said integrated circuit portions so far described, covering all three of the polysilicon deposits, all of which are coplanar with each other, (f) forming a hole in said passivation layer to each of said second and third coplanar polysilicon deposits, the holes being of identical depth, and (g) providing metal plug contacts extending into each said hole that are identical in height.
Claim 3
Dependent Claim
40 words
The method of claim 1, wherein between steps (b) and (c) there is a step of providing a gate oxide layer that in step (c) is overlaid by some of said polysilicon deposits and is etched away between the gates.
Claim 4
Dependent Claim
44 words
The method of claim 1 wherein step (d) comprises coating with a refractive metal and the coating with amorphous silicon, followed by reaction between these two coatings to provide a conductive silicide and etching the silicide to limit the extent of said conductive path.
Claim 5
Independent Claim
246 words
A method of forming an integrated circuit chip comprising the steps of: (a) forming a substrate having a planar surface, (b) forming on said substrate at least two field oxide regions. separated from each other and having two separated diffusion regions, namely a source diffusion region and a drain diffusion region, all coplanar with said planar surface, (c) forming at least three separate coplanar polysilicon deposits, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, with spaces between the polysilicon deposits, (d) forming a highly conductive path over each said polysilicon deposit, the one over said gate being confined thereto, and the others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, (e) forming a first dielectric layer covering those integrated circuit portions below the top level of the polysilicon deposits, all of which are coplanar with each other, and with the top level of the polysilicon deposits, (f) forming a second dielectric layer over said first layer and over all portions of said integrated circuit above said first dielectric layer, (g) removing portions of said second dielectric layer over the highly conductive paths that overlie said gate and said polysilicon deposits to provide wide gaps, larger than the same of said polysilicon deposits, (h) providing metal contacts extending into the said gaps.
Claim 6
Independent Claim
246 words
A method of forming an integrated circuit chip comprising the steps of: (a) forming a substrate having a planar surface, (b) forming on said substrate at least two field oxide regions. separated from each other and having two separated diffusion regions, namely a source diffusion region and a drain diffusion region, all coplanar with said planar surface, (c) forming at least three separate coplanar polysilicon deposits, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, with spaces between the polysilicon deposits, (d) forming a highly conductive path over each said polysilicon deposit, the one over said gate being confined thereto, and the others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, (e) forming a first dielectric layer covering those integrated circuit portions below the top level of the polysilicon deposits, all of which are coplanar with each other, and with the top level of the polysilicon deposits, (f) forming a second dielectric layer over said first layer and over all portions of said integrated circuit above said first dielectric layer, (g) removing portions of said second dielectric layer over the highly conductive paths that overlie said gate and said polysilicon deposits to provide wide gaps, larger than the same of said polysilicon deposits, (h) providing metal contacts extending into the said gaps.
Claim 7
Dependent Claim
41 words
The method of claim 4, wherein between steps (b) and (c) there is a step of providing a a gate oxide layer that in step (c) is overlaid by some of said polysilicon deposits and is etched away between the gates.
Claim 8
Dependent Claim
44 words
The method of claim 4 wherein step (d) comprises coating with a refractive metal and the coating with amorphous silicon, followed by reaction between these two coatings to provide a conductive silicide and etching the silicide to limit the extent of said conductive path.
Claim 9
Dependent Claim
33 words
The method of claim 4 wherein said step (g) comprises etching with an etchant that acts at least ten times more rapidly on said second dielectric layer than on said first dielectric layer.
Claim 10
Dependent Claim
50 words
The method of claim 4 wherein said first dielectric layer is selected from the group consisting of phosphosilicate glass, borosilicate phosphate glass, TEOS, and nitrides, and second dielectric layer is selected from the groups consisting of polyimide, plasma enhanced nitride, and spin-on glass and said etchant is a plasma etchant.
Claim 11
Dependent Claim
188 words
An integrated circuit chip comprising: a substrate having a planar surface, at least two field oxide regions on said substrate separated from each other, each having a separate diffusion regions, one a source diffusion region and one a drain diffusion region, all coplanar with said planar surface, at least three separate coplanar polysilicon deposits, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, a highly conductive path over each said polysilicon deposit, one over said gate and confined thereto, and two others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, a passivation layer over all of said integrated circuit portions so far described, covering all three of the polysilicon deposits, all of which are coplanar with each other said passivation layer having an opening therethrough to each of said second and third coplanar polysilicon deposits, and metal contacts of identical length extending into each said opening into contact with a said highly conductive path.
Claim 12
Dependent Claim
188 words
An integrated circuit chip comprising: a substrate having a planar surface, at least two field oxide regions on said substrate separated from each other, each having a separate diffusion regions, one a source diffusion region and one a drain diffusion region, all coplanar with said planar surface, at least three separate coplanar polysilicon deposits, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, a highly conductive path over each said polysilicon deposit, one over said gate and confined thereto, and two others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, a passivation layer over all of said integrated circuit portions so far described, covering all three of the polysilicon deposits, all of which are coplanar with each other said passivation layer having an opening therethrough to each of said second and third coplanar polysilicon deposits, and metal contacts of identical length extending into each said opening into contact with a said highly conductive path.
Claim 13
Dependent Claim
211 words
An integrated circuit chip comprising: a substrate having a planar surface, at least two field oxide regions on said substrate separated from each other and having two separated diffusion regions, namely a source diffusion region and a drain diffusion region, all coplanar with said planar surface, at least three separate polysilicon deposits coplanar with each other, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, a highly conductive path over each said polysilicon deposit, the one over said gate being confined thereto, and the others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, a first dielectric layer covering those integrated circuit portions below the top level of the polysilicon deposits, all of which are coplanar with each other, there being spaces between portions of said first dielectric layer, a second dielectric layer over said first layer and over all portions of said integrated circuit above said first dielectric layer, with spaces providing openings therethrough over the highly conductive paths that overlie said gate and said polysilica deposits, and metal contacts of identical length extending into said spaces.
Claim 14
Dependent Claim
211 words
An integrated circuit chip comprising: a substrate having a planar surface, at least two field oxide regions on said substrate separated from each other and having two separated diffusion regions, namely a source diffusion region and a drain diffusion region, all coplanar with said planar surface, at least three separate polysilicon deposits coplanar with each other, comprising a gate deposit bridging over and between said two separated source and drain diffusion regions, and second and third deposits, each over one of said two field oxide regions, a highly conductive path over each said polysilicon deposit, the one over said gate being confined thereto, and the others extending from a top of a said polysilicon deposit down to and in good electrical contact with its adjacent diffusion region, a first dielectric layer covering those integrated circuit portions below the top level of the polysilicon deposits, all of which are coplanar with each other, there being spaces between portions of said first dielectric layer, a second dielectric layer over said first layer and over all portions of said integrated circuit above said first dielectric layer, with spaces providing openings therethrough over the highly conductive paths that overlie said gate and said polysilica deposits, and metal contacts of identical length extending into said spaces.
References Cited (Backward Citations)
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