EP0288860A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Fast flush for a first-in first-out memory
Assignee: Advanced Micro Devices Inc
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Filing: 1988-04-18
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Granted: —
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Expires: 2008-04-18
Abstract
Abstract In a memory circuit including a write bit-line (32, 36) for writing data into a memory cell (10), and a read bit-line (34, 38) for reading data from the cell, a transistor (50, 52) is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied by an AND gate (44) to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.
Inventors
- 👤 Stuart T. Auvinen
- 👤 Barry A. Hoberman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 13:42
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G11; G11C; G11C7/00; G11C7/12; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
84 words
A circuit for reducing the fall-through delay of data in a memory cell (10), comprising a write bit-line (32) connected with the memory cell for communicating data to the cell and a read bit-line (34) connected with the memory cell for communicating data from the cell, characterised by means (44,50) selectively connecting the write bit-line with the read bit-line independent of the memory cell so that data carried by the write bit-line can be communicated to the read bit-line independent of the memory cell.
Claim 2
Dependent Claim
84 words
A circuit for reducing the fall-through delay of data in a memory cell (10), comprising a write bit-line (32) connected with the memory cell for communicating data to the cell and a read bit-line (34) connected with the memory cell for communicating data from the cell, characterised by means (44,50) selectively connecting the write bit-line with the read bit-line independent of the memory cell so that data carried by the write bit-line can be communicated to the read bit-line independent of the memory cell.
Claim 3
Dependent Claim
36 words
A circuit according to claim 1, wherein the means for selectively connecting the write bit-line to the read bit-line independent of the memory cell comprise switch means operatively associated with the write bit-line and read bit-line.
Claim 4
Dependent Claim
57 words
A circuit according to claim 2, wherein the switch means comprises an MOS transistor (50) having a drain connected to the write bit-line, a source connected to the read bit-line, and a gate (44) to which a signal may be applied for selectively providing communication through said MOS transistor between the write bit-line and the read bit-line.
Claim 5
Dependent Claim
25 words
A circuit according to any one of claims 1 to 3, comprising a sense amplifier (60) connected with the read bit-line for receiving data therefrom.
References Cited (Backward Citations)
No citation records indexed.
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