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EP0288636A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Network communications adapter

Assignee: Network Systems Corp
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Filing: 1987-09-16
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Granted: —
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Expires: 2007-09-16
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Abstract

Abstract A network communications adapter for interconnecting a plurality of digital computing resources for mutual data exchange in which a high performance, large capacity common memory is provided with a pair of external buses which allows multiple processors to store information in and read information from the common memory. The common memory is configured into two banks, each bank operating independently and concurrently under control of bus switching logic with separate address, control and data buses. The common memory typically provides 400 megabits per second of bandwidth to the multiple attached thirty-­two and sixteen bit processors which may be coupled either to both buses simultaneously or individually to the two buses. The bus switching logic then allocates all of the available bandwidth to the individual processors coupled to the buses based upon a predetermined profile established at the time of system installation. Also included in the bus switch logic is circuitry for broad­casting a processor I.D., whereby only a particular processor assigned the same identifier will be afforded an access slot time during which communication over the dual bus structure can take place. One of the inter­connected processors is designated as the node controller and it includes circuitry and software for implementing interprocessor interrupt handling and storage protection functions. Others of the plurality of processors coupled to the two memory buses provide input/output interfaces for host computers, digital peripheral devices, communications trunks or buses, or to wireless links for more remote communication.

Inventors

  • 👤 Donald J. Humphrey
  • 👤 Wayne A. Peterson
  • 👤 James P. Hughes
  • 👤 Waye R. Roiger

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-23 16:13
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F12/00; G06F12/14; G06F12/1458; G06F12/1466; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663; G06F13/20; G06F13/24; G06F13/26

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 194 words
A communications network adapter comprising: (a) central random access buffer memory means for storing data at addressable locations, said buffer memory means for storing data at addressable locations, said buffer memory means being partitioned into first and second independently and concurrently operating interleaved banks; (b) first and second common bus means selectively connectable on an alternating basis to said first and second banks for providing, on a time multiplexed basis, address representing signals and data representing signals to said buffer memory for storing said data representing signals therein; (c) first and second read data bus means selectively connectable on an alternating basis to said two banks for carrying data representing signals read out from said memory means; (d) a plurality of processing means individually coupled to said first and second common buses and read data buses, selected ones of said plurality of processing means having input/output means for communication with digital devices connected thereto; and (e) node control means including memory access control means for synchronously and cyclicly connecting alternate ones of said first and second banks to said first and second common bus means and said first and second read data bus means.
Claim 2
Dependent Claim 194 words
A communications network adapter comprising: (a) central random access buffer memory means for storing data at addressable locations, said buffer memory means for storing data at addressable locations, said buffer memory means being partitioned into first and second independently and concurrently operating interleaved banks; (b) first and second common bus means selectively connectable on an alternating basis to said first and second banks for providing, on a time multiplexed basis, address representing signals and data representing signals to said buffer memory for storing said data representing signals therein; (c) first and second read data bus means selectively connectable on an alternating basis to said two banks for carrying data representing signals read out from said memory means; (d) a plurality of processing means individually coupled to said first and second common buses and read data buses, selected ones of said plurality of processing means having input/output means for communication with digital devices connected thereto; and (e) node control means including memory access control means for synchronously and cyclicly connecting alternate ones of said first and second banks to said first and second common bus means and said first and second read data bus means.
Claim 3
Dependent Claim 108 words
The communications network adapter as in Claim 1 wherein said node control means includes means for broadcasting a processor slot I.D. number to each of said plurality of processing means coupled to said first and second common buses for selectively allocating the effective bandwidth of said first and second common buses and said first and second read data buses to said plurality of processing means, only the one of said plurality of processing means having a processor I.D. corresponding to the broadcast processor slot I.D. being able to exchange data representing signals with said central memory means during a predetermined time interval established by said node control means.
Claim 4
Dependent Claim 98 words
The communications network adapter as in Claim 1 and further including storage protection logic in said node control means individually associated with each of said first and second banks, said storage protection logic comparing said address representing signals originating from one of said plurality of processing means and present on said first and second common bus means to a predetermined key I.D. assigned to said one of said plurality of processing means for generating a fault interrupt signal when access to an unauthorized range of central memory addresses for said one of said plurality of processors is attempted.
Claim 5
Dependent Claim 117 words
The communications network adapter as in Claim 2 wherein said means for broadcasting comprises: (a) programmable read-only memory slot means for storing a plurality of processor I.D. words defining system profiles; (b) addressing means including counter means and preset switching means coupled to said programmable read-­only memory for reading out said words defining system profiles as said counter means is advanced; (c) means for applying regularly occurring timing signals to said counter means to sequentially advance said counter means to read out processor slit I.D. words from said programmable read-only memory in a desired sequence; and (d) a processor slot I.D. bus coupling the output from said programmable read-only memory means to said plurality of processing means.
Claim 6
Dependent Claim 161 words
The communications network adapter as in Claim 1 and further including interrupt control means in said node control means for generating a timed sequence of interrupt identifier codes; interrupt bus means coupling said interrupt control means to said plurality of processing means for transmitting said interrupt identifier codes to each of said plurality of processing means; means in each of said processing means responsive to a different one of said interrupt identifier codes assigned to that processing means for inviting the particular processing means responding to its interrupt identifier code to place an interrupt request and a processor identifier code for a destination processor to which said interrupt request is directed on said interrupt bus means; and interrupt processor means coupled to said interrupt bus means for receiving said interrupt request and said processor identifier code of the destination processor for routing interrupt data to a predetermined one of said plurality of processing means in accordance with a predetermined priority assignment.
Claim 7
Dependent Claim 43 words
The communications network adapter as in Claim 5 wherein said interrupt processor includes a dedicated storage means for storing at addressable locations route maps containing priority levels, destination and origin information of the interrupting and interrupted ones of said plurality of processing means.

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