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EP0288152A2
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A picture-in-picture video signal generator
Assignee: RCA Licensing Corp
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Filing: 1988-03-22
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Granted: —
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Expires: 2008-03-22
Abstract
Abstract A picture-in-picture video signal generator includes a source (50) of an auxiliary video signal, and a producer (60) of successive samples representing the auxiliary video signal. A self-sequencing memory (70) includes a data input terminal coupled to the producer ofauxiliary video samples; a write address input terminal, for receiving an initial write address; a data output terminal; and a read address input terminal for receiving an initial read address. Write control circuitry (80,90) is coupled to the write address terminal of the self-sequencing. memory, and generates initial write addresses in synchronism with horizontal line intervals of the auxiliary video signal. A source (10) of a main video signal is also provided. Read control circuitry (100,110) is coupled to the read address terminal of the self-sequencing memory, and generates initial read addresses in synchronism with horizontal line intervals of the main video signal. Means (20,30) are provided for combining the main video signal with samples from the self-sequencing memory to form a video signal representing a picture-in- picture image.
Inventors
- 👤 Robert Francis Casey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 05:32
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/445; H04N5/45
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
165 words
A picture-in-picture video signal generator, comprising: a source (50) of an auxiliary video signal; means (60) for producing successive samples representing said auxiliary video signal; a self-sequencing memory (70), having a data input terminal coupled to said sample producer, a data output terminal and input terminal means for receiving initial read and write addresses; write control circuitry (80,90) coupled between said source of said auxiliary video signal and said input terminal means of said self-sequencing memory, for producing successive initial write address signals, in synchronism with horizontal line intervals of said auxiliary video signal; a source (10) of a main video signal; read control circuitry (100,110) coupled between said main video signal source and said input terminal means of said self-sequencing memory, for producing successive initial read address signals, in synchronism with horizontal line intervals of said main video signal; and means (20,30) coupled to said data output terminal of said self-sequencing memory and said main video signal source for generating a picture-in-picture video signal.
Claim 2
Dependent Claim
165 words
A picture-in-picture video signal generator, comprising: a source (50) of an auxiliary video signal; means (60) for producing successive samples representing said auxiliary video signal; a self-sequencing memory (70), having a data input terminal coupled to said sample producer, a data output terminal and input terminal means for receiving initial read and write addresses; write control circuitry (80,90) coupled between said source of said auxiliary video signal and said input terminal means of said self-sequencing memory, for producing successive initial write address signals, in synchronism with horizontal line intervals of said auxiliary video signal; a source (10) of a main video signal; read control circuitry (100,110) coupled between said main video signal source and said input terminal means of said self-sequencing memory, for producing successive initial read address signals, in synchronism with horizontal line intervals of said main video signal; and means (20,30) coupled to said data output terminal of said self-sequencing memory and said main video signal source for generating a picture-in-picture video signal.
Claim 3
Dependent Claim
47 words
The picture-in-picture video signal generator, of Claim 1, wherein said read control circuitry comprises a synchronization component separator coupled to said main video signal source, for producing a main horizontal synchronization signal; and produces successive initial read address signals in synchronism with said main horizontal synchronization signal.
Claim 4
Dependent Claim
151 words
The picture-in-picture video signal generator, of Claim 2, wherein: said synchronization component separator also produces a main vertical synchronization signal; and said read control circuity further includes a read address generator comprising: a line address counter, responsive to said main horizontal synchronization signal, and having an enable input terminal, for producing a signal representing said initial read address in response to a signal at said enable input terminal; a vertical enable signal generator, responsive to said main horizontal and vertical synchronization signals, and having an output terminal coupled to said enable terminal of said line address counter, for generating said enable signal when currently scanned lines of said main video signal are to have auxiliary image information inserted into them; and means responsive to said main vertical synchronization signal, for setting said line address counter to a predetermined value at the beginning of a vertical scan of said main video signal.
Claim 5
Dependent Claim
91 words
The picture-in-picture video signal generator of Claim 3 wherein said vertical enable signal generator comprises: first means responsive to said main horizontal synchronization signal for counting to a predetermined number representing the starting line in said picture-in-picture video signal for inserting auxiliary video signal information; second means responsive to said main horizontal synchronization signal for counting to a predetermined number representing the number of lines of auxiliary video signal to be inserted into said picture-in-picture video signal; and means coupled to said first and second means for producing said enable signal.
Claim 6
Dependent Claim
20 words
The picture-in-picture video signal generator of Claim 4, wherein said first and second means in combination comprise a frequency divider.
Claim 7
Dependent Claim
23 words
The picture-in-picture video signal generator of Claim 5, wherein said enable signal producing means comprises a ring counter responsive to said frequency divider.
Claim 8
Dependent Claim
141 words
The picture-in-picture video signal generator of Claim 3, wherein: memory locations of said self-sequencing memory are allocated as a plurality of blocks, each of which can store one field of auxiliary video signal information; and said line address counter setting means comprises means for producing a signal representing the block of said self-sequencing memory from which samples representing a previously stored field of said auxiliary video signal are to be retrieved; a block start address generator, coupled to said block representative signal producing means, for producing a signal representing the initial read address of the first line of said block of said self-sequencing memory; and means for setting said line address counter to said initial read address of said first line at the beginning of the time period of insertion of said auxiliary video signal information into said picture-in-picture video signal.
Claim 9
Dependent Claim
19 words
The picture-in-picture video signal generator of Claim 7, wherein said block representative signal producing means comprises a delay circuit.
Claim 10
Dependent Claim
49 words
The picture-in-picture video signal generator of any preceding claim wherein said write control circuitry comprises: a synchronization component separator, coupled to said auxiliary video signal source, for producing an auxiliary horizontal synchronization signal, and produces said successive initial write address signals in synchronism with said auxiliary horizontal synchronization signal.
Claim 11
Dependent Claim
111 words
The picture-in-picture video signal generator of Claim 8, wherein: said synchronization component separator further produces an auxiliary vertical synchronization signal; and said write control circuitry further includes a write address generator comprising: a frequency divider responsive to said auxiliary horizontal synchronization signal, and having an output terminal; a line address counter having a clock input terminal coupled to said output terminal of said frequency divider and an output terminal for producing at least a component of said initial write address; and means, responsive to said auxiliary vertical synchronization signal, for setting said line address counter to a predetermined count at the beginning of a vertical scan of said auxiliary video signal.
Claim 12
Dependent Claim
42 words
The picture-in-picture video signal generator of Claim 3 or 10, wherein said line address counter comprises: a latch for producing lower significance bits of said initial write address; and a binary counter for producing higher significance bits of said initial write address.
Claim 13
Dependent Claim
140 words
The picture-in-picture video signal generator of Claim 10 or 11, wherein: memory locations of said self-sequencing memory are allocated as a plurality of blocks, each of which can store one field of auxiliary video signal information; and said line address counter setting means comprises a field counter responsive to said auxiliary vertical synchronization signal for producing a signal representing the block of said self-sequencing memory into which samples representing a current field of said auxiliary video signal is to be written; a block start address generator, coupled to said field counter, for producing a signal representing the initial write address of the first line of said block of said self-sequencing memory; and means for setting said line address counter to said initial write address of said first line at the beginning of said current field of said auxiliary video signal.
References Cited (Backward Citations)
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