Liquid crystal display device and method of driving the same

Claim 2

A liquid crystal display panel including a first substrate, a second substrate having a transparent conduc­tive film (38) thereon, and a liquid crystal layer sandwiched between the first substrate and the second substrate, the first substrate having thereon a plurality of data lines (21), a plurality of gate lines (22), a plurality of pixel electrodes (9) each formed in the vicinity of a position where a data line and a gate line cross each other, and a plurality of thin film transistors (4) each formed at a position where a data line and a gate line cross each other, for driving a pixel electrode, the liquid crystal display panel comprising: a capacitor (7) whose electrodes are formed of a portion of the pixel electrode (9) connected to a thin film transistor (4) which is driven by a gate line (2), and a portion of the next gate line (3); and gate voltage generating means (62, 72) for controlling the voltage of each gate line in such a manner that, when a gate driving voltage applied to a gate line (2) for driving a thin film transistor (4) is changed by an amount v₁ to turn off the thin film transistor, a voltage change (v₁ + v₂) in a gate driving voltage applied to the next gate line (3) is generated in a direc­tion opposite to the direction of the voltage change v₁ (where, v₁ > 0 and v₂ > 0).

Claim 3

A liquid crystal display panel including a first substrate, a second substrate having a transparent conduc­tive film (38) thereon, and a liquid crystal layer sandwiched between the first substrate and the second substrate, the first substrate having thereon a plurality of data lines (21), a plurality of gate lines (22), a plurality of pixel electrodes (9) each formed in the vicinity of a position where a data line and a gate line cross each other, and a plurality of thin film transistors (4) each formed at a position where a data line and a gate line cross each other, for driving pixel electrode, the liquid crystal display panel comprising: a capacitor (7) whose electrodes are formed of a portion of the pixel electrode (9) connected to a thin film transistor (4) which is driven by the i-th gate line (2), and a portion of the (i+1)th gate line (3); and gate voltage generating means (62, 72) for controlling the voltage of each gate line in such a manner that, in synchronism with a voltage change v₁ in a gate driving voltage applied to the i-th gate line (2) for turning off a thin film transistor (4) driven by the i-th gate line, a voltage change (v₁ + v₂) in a gate driving voltage applied to the (i+1)th gate line (3) is generated in a direction opposite to the direction of the voltage change v₁ (where v₁ > 0 and v₂ > 0).

Claim 4

A liquid crystal display panel including a first substrate, a second substrate having a transparent conduc­tive film (38) thereon, and a liquid crystal layer sandwiched between the first substrate and the second substrate, the first substrate having thereon a plurality of data lines (21), a plurality of gate lines (22), a plurality of pixel electrodes (9) each formed in the vicinity of a position where a data line and a gate line cross each other, and a plurality of thin film transistors (4) each formed at a position where a data line and a gate line cross each other, for driving pixel electrode, the liquid crystal display panel comprising: a capacitor (7) whose electrodes are formed of a portion of the pixel electrode (9) connected to a thin film transistor (4) which is driven by the i-th gate line (2), and a portion of the (i+1)th gate line (3); and gate voltage generating means (62, 72) for controlling the voltage of each gate line in such a manner that, in synchronism with a voltage change v₁ in a gate driving voltage applied to the i-th gate line (2) for turning off a thin film transistor (4) driven by the i-th gate line, a voltage change (v₁ + v₂) in a gate driving voltage applied to the (i+1)th gate line (3) is generated in a direction opposite to the direction of the voltage change v₁ (where v₁ > 0 and v₂ > 0).

Claim 5

A liquid crystal panel including a first sub­strate, a second substrate having a transparent conductive film (38) thereon, and a liquid crystal layer sandwiched between the first substrate and the second substrate, the first substrate having thereon a plurality of data lines (21), a plurality of gate lines (22), a plurality of pixel electrodes (9) each formed in the vicinity of a position where a data line and a gate line cross each other, and a plurality of thin film transistors (4) each formed at a position where a data line and a gate line cross each other, for driving a pixel electrode, the liquid crystal display panel comprising means for applying each gate line with a gate driving voltage waveform capable of cancelling out the capacitive coupling to a first pixel electrode and reducing noise which is generated at a second pixel electrode by said cancellation of the capacitive coupling of the gate driving voltage to the first pixel electrode voltage.

Claim 6

A liquid crystal panel including a first sub­strate, a second substrate having a transparent conductive film (38) thereon, and a liquid crystal layer sandwiched between the first substrate and the second substrate, the first substrate having thereon a plurality of data lines (21), a plurality of gate lines (22), a plurality of pixel electrodes (9) each formed in the vicinity of a position where a data line and a gate line cross each other, and a plurality of thin film transistors (4) each formed at a position where a data line and a gate line cross each other, for driving a pixel electrode, the liquid crystal display panel comprising means for applying each gate line with a gate driving voltage waveform capable of cancelling out the capacitive coupling to a first pixel electrode and reducing noise which is generated at a second pixel electrode by said cancellation of the capacitive coupling of the gate driving voltage to the first pixel electrode voltage.

Claim 9

The invention as claimed in Claim 2 or 4, wherein the voltage change (v₁ + v₂) in the gate driving voltage ap­plied to the (i+1)th gate line (3) is generated simultaneously with the voltage change v₁ in the gate driving voltage ap­plied to the i-th gate line (2).

Claim 10

The invention as claimed in Claim 2 or 4, wherein the voltage (v₁ + v₂) in the gate driving voltage applied to the (i+1)th gate line (3) is generated when a time less than the selection time of the thin film transistor (4) has elapsed after the voltage change v₁ in the gate driving voltage ap­plied to the i-th gate line (2).

Claim 11

The invention as claimed in Claim 1, 2 or 4, wherein the capacitor C add of the capacitor (7) satisfies the following formula: C add ≒ (v₁/v₂) · C gs where C gs indicates the parasitic gate-source capacitance of the thin film transistor (4).