EP0287334A2
Expired / Lapsed
EP
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High availability cache memory
Assignee: Prime Computer Inc
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Filing: 1988-04-12
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Granted: —
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Expires: 2008-04-12
Abstract
Abstract A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.
Inventors
- 👤 Brian Lefsky
- 👤 Ellen Mary Natusch
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 01:45
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F12/12; G06F12/121; G06F12/126; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F2212/00; G06F2212/10; G06F2212/1032
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
204 words
A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, said status field including a force bit which indicates a defective cache cell when it is set; read means for reading data from said cache memory including means for addressing a prescribed set of said cache cells, means for comparing said tag field for each cache cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to the cleared state of said force bit and to said hit signal for enabling one of the cache cells in said prescribed set to provide its data field to said central processing unit; and write means for storing data from said main memory in said prescribed set of cache cells.
Claim 2
Dependent Claim
204 words
A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, said status field including a force bit which indicates a defective cache cell when it is set; read means for reading data from said cache memory including means for addressing a prescribed set of said cache cells, means for comparing said tag field for each cache cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to the cleared state of said force bit and to said hit signal for enabling one of the cache cells in said prescribed set to provide its data field to said central processing unit; and write means for storing data from said main memory in said prescribed set of cache cells.
Claim 3
Dependent Claim
36 words
A cache memory as defined in claim 1 wherein said write means includes means for selectively setting or clearing said force bit for each cache cell when the respective cache cell is found to be defective.
Claim 4
Dependent Claim
73 words
A cache memory as defined in claim 2 wherein said read means further includes means for checking the parity of said data field and of said tag field and providing a parity error signal when correct parity is not found for a cache cell, and wherein said output enable means is responsive to said parity error signal to inhibit the respective cache cell from providing its data field to said central processing unit.
Claim 5
Dependent Claim
26 words
A cache memory as defined in claim 3 wherein said status field further includes an update bit which indicates the update status of said cache cell.
Claim 6
Dependent Claim
47 words
A cache memory as defined in claim 4 wherein said write means further includes replacement selection means responsive to the update bit for each of said cache cells in the prescribed set for selecting which cache cell of the prescribed set is to have its data replaced.
Claim 7
Dependent Claim
33 words
A cache memory as defined in claim 5 wherein said write means further includes means for changing the state of said update bit each time the data in said cache cell is replaced.
Claim 8
Dependent Claim
44 words
A cache memory as defined in claim 5 wherein said write means further includes means for changing the state of said update bit each time the data in said cache cell is replaced unless the cache cell was modified on a previous store cycle.
Claim 9
Dependent Claim
34 words
A cache memory as defined in claim 5 wherein said replacement selection means is further responsive to said force bit to avoid storing data in any cache cell which has its force bit set.
Claim 10
Dependent Claim
18 words
A cache memory as defined in claim 5 wherein said replacement selection means employs a first-in first-out algorithm.
Claim 11
Dependent Claim
226 words
A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, said status field including an update bit which indicates the update status of the cache cell; read means for reading data from said cache memory including means for addressing a prescribed set of said cache cells, means for comparing said tag field for each cache cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to said hit signal for enabling one of the cache cells in said prescribed set to provide its data field to said central processing unit; and write means for storing data from said main memory in said prescribed set of cache cells including replacement selection means responsive to the update bit for each of said cache cells in the prescribed set for selecting which cache cell of the prescribed set is to have its data replaced.
Claim 12
Dependent Claim
226 words
A set associative cache memory for use as a buffer between a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, said status field including an update bit which indicates the update status of the cache cell; read means for reading data from said cache memory including means for addressing a prescribed set of said cache cells, means for comparing said tag field for each cache cell in said prescribed set with a physical address and for providing a hit signal when one of the tag fields and said physical address are equal, and output enable means responsive to said hit signal for enabling one of the cache cells in said prescribed set to provide its data field to said central processing unit; and write means for storing data from said main memory in said prescribed set of cache cells including replacement selection means responsive to the update bit for each of said cache cells in the prescribed set for selecting which cache cell of the prescribed set is to have its data replaced.
Claim 13
Dependent Claim
33 words
A cache memory as defined in claim 10 wherein said write means further includes means for changing the state of said update bit each time the data in said cache cell is replaced.
Claim 14
Dependent Claim
44 words
A cache memory as defined in claim 10 wherein said write means further includes means for changing the state of said update bit each time the data in said cache cell is replaced unless the cache cell was modified on a previous store cycle.
Claim 15
Dependent Claim
54 words
A cache memory as defined in claim 10 wherein said status field further includes a force bit which indicates a defective cache cell when it is set and wherein said replacement selection means is further responsive to said force bit to avoid storing data in any cache cell which has its force bit set.
Claim 16
Dependent Claim
139 words
A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, each status field including a force bit which indicates a defective state of said cache cell; read means for reading data from said cache cells; write means for storing data in said cache cells; and means responsive to said force bit indicating a defective state of said cache cell for suppressing data read from said defective cache cell and for preventing storing data in said defective cache cell.
Claim 17
Dependent Claim
139 words
A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, each status field including a force bit which indicates a defective state of said cache cell; read means for reading data from said cache cells; write means for storing data in said cache cells; and means responsive to said force bit indicating a defective state of said cache cell for suppressing data read from said defective cache cell and for preventing storing data in said defective cache cell.
Claim 18
Dependent Claim
132 words
A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, each status field including an update bit which indicates the update status of said cache cell; read means for reading data from said cache cells; write means for storing data in said cache cells; and means responsive to the update bits in a set of cache cells for selecting a cache cell of said set for said write means to modify.
Claim 19
Dependent Claim
132 words
A high availability set associative cache memory for buffering a main memory and a central processing unit, said cache memory comprising: multiple sets of cache memory cells contained in a plurality of cache memory elements, each of the cache cells including a data field, a tag field and a status field, and each of the sets of cache cells including a commonly addressed cache cell from each of said memory elements, each status field including an update bit which indicates the update status of said cache cell; read means for reading data from said cache cells; write means for storing data in said cache cells; and means responsive to the update bits in a set of cache cells for selecting a cache cell of said set for said write means to modify.
References Cited (Backward Citations)
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