Patent US5888080A successfully refreshed from Google Patents.
EP0287301A2
Expired / Lapsed
EP
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Input/output system for multiprocessors
Assignee: Tandem Computers Inc
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Filing: 1988-04-11
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Granted: —
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Expires: 2008-04-11
Abstract
Abstract In a digital computer system which employs a plurality of host processors (33), at least two system buses (35) and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels (109) is shared. The device controller (41) employs a first port controller (43-0) having a first ownership latch, a second port controller (43-1) having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controlIer which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI) (111), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.
Inventors
- 👤 David Lee Burnick
- 👤 Kenneth Kin Chan
- 👤 Wing Ming Chan
- 👤 Yie-Fong Dan
- 👤 Duc Manh Hoang
- 👤 Zubair Hussain
- 👤 Geoffrey Igantius Iswandhi
- 👤 James Edward Korpi
- 👤 Martin William Sanner
- 👤 Jay Allyn Zwagerman
- 👤 Steven Gary Silverman
- 👤 James Emerson Smith
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/10; G06F13/12; G06F13/122; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
114 words
For use in a digital computer system, a device controller comprising: a first port-input/output controller means coupled to a first input/output channel bus and a second port-input/output controller coupled to a second input/output channel bus; said port-input/output controller means having: a first ownership latch means for granting ownership of said device controller to a first host processor, and a second ownership latch means operative independently of said first ownership latch means for granting ownership of said device controller to a second host processor independently of said first port input/output controller, thereby to provide multiple data paths between one of said first or second host processors and any peripheral devices coupled to said device controller.
Claim 2
Dependent Claim
114 words
For use in a digital computer system, a device controller comprising: a first port-input/output controller means coupled to a first input/output channel bus and a second port-input/output controller coupled to a second input/output channel bus; said port-input/output controller means having: a first ownership latch means for granting ownership of said device controller to a first host processor, and a second ownership latch means operative independently of said first ownership latch means for granting ownership of said device controller to a second host processor independently of said first port input/output controller, thereby to provide multiple data paths between one of said first or second host processors and any peripheral devices coupled to said device controller.
Claim 3
Dependent Claim
65 words
The device controller according to claim 1 further comprising: a peripheral device-input/output controller means; and multiplexer means coupled to said peripheral device-input/output controller means on one end and coupled to a first SCSI bus and to a second SCSI bus on the other end thereby to provide for connection to either said first SCSI bus or to said second SCSI bus through said device controller.
Claim 4
Dependent Claim
167 words
The device controller according to claim 2 further comprising: a first bus operative at a first clock rate; a dedicated microprocessor means having control over said first bus (the MPU bus); a second synchronous bus operative at a second clock rate, different from said first clock rate; a multiple-channel direct memory access (DMA) controller means comprising a state machine, said DMA controller means having control over said second synchronous bus (the data buffer bus) and control over and access to said first and second input/output channel buses for arbitrating access to said first bus; and a first bus switch coupled between said first bus and said second synchronous bus for communicating first information on said first synchronous bus at said first clock rate to said second synchronous bus at said second clock rate and second information on said second synchronous bus at said second clock rate to said first bus at said first clock rate under control of said DMA controller and upon request of said MPU.
Claim 5
Dependent Claim
125 words
The device controller according to claim 1 further comprising: a first bus ; a dedicated microprocessor means having control over said first bus (the MPU bus); a second bus; a multiple-channel direct memory access (DMA) controller means comprising a state machine, said DMA controller means having control over said second bus (the data buffer bus) and control over and access to said first and second input/output channel buses for arbitrating access to said first bus; and a first bus switch coupled between said first bus and said second bus for communicating first information on said first bus to said second bus and second information on said second bus at to said first bus under control of said DMA controller and upon request of said MPU.
Claim 6
Dependent Claim
167 words
The device controller according to claim 1 further comprising: a first bus operative at a first clock rate; a dedicated microprocessor means having control over said first synchronous bus (the MPU bus); a second synchronous bus operative at a second clock rate, different from said first clock rate; a multiple-channel direct memory access (DMA) controller means comprising a state machine said DMA controller means having control over said second synchronous bus (the data buffer bus) and control over and access to said first and second input/output channel buses for arbitrating access to said first bus; and a first bus switch coupled between said first bus and said second synchronous bus for communicating first information on said first bus at said first clock rate to said second synchronous bus at said second clock rate and second information on said second synchronous bus at said second clock rate to said first bus at said first clock rate under controI of said DMA controller and upon request of said MPU.
Claim 7
Dependent Claim
81 words
The device controller according to claim 5, wherein said DMA controller comprises a programmabIe state machine defining by alternating time allocation a first channel and a second channel on said second synchronous bus, said programmable state machine including means for arbitrating time allocation between said first channel and said second channel for data transfer on said second synchronous bus, and for allocating time on said second synchronous bus to said microprocessor means at a lower priority than for said data transfer.
Claim 8
Dependent Claim
75 words
The device controller according to claim 5, wherein said programmable state machine further comprises means imposing a maximum latency between a data request and a data acknowledge issued by, said state machine of no more than two bus cycles on any channel and wherein maximum latency between a bus request issued by said microprocessor and a bus grant issued by said state machine is dependent upon load of said first channel and said second channel.
Claim 9
Dependent Claim
33 words
The device controller according to claim 5, wherein said DMA controller further includes means for generating channel address values in less than one clock period for assuring timely generation of channel address values.
Claim 10
Dependent Claim
21 words
The device controller according to claim 5, further including register means and program means for programming said DMA controller during operation.
Claim 11
Dependent Claim
39 words
The device controller according to claim 9, wherein said DMA controller further includes means for programming chaining of related data blocks for continuous transfer of priority data on one of said channels independent of the other of said channels.
Claim 12
Dependent Claim
26 words
The device controller according to claim 10, wherein said DMA controller further includes programmable means providing for direct data transfer without intervention of said microprocessor means.
Claim 13
Dependent Claim
45 words
The device controller according to claim 5, wherein said DMA controller further includes means for predicting address parity, means for generating address parity and means for comparing predicted parity with generated parity in order to verify that said DMA controller is generating correct sequential addresses.
Claim 14
Dependent Claim
89 words
The device controller according to claim 5 wherein said first bus switch comprises: latch means for latching data from said second synchronous bus for reading by said microprocessor means coupled to said first bus; three-state buffer means for buffering data sent from said first bus to said second synchronous bus; and delay means coupled to an enable input of said three-state buffer means for imposing an interval between successive data transfers via said three-state buffer in synchronism with a selected one of said channels of said second bus means.
Claim 15
Dependent Claim
81 words
The device controller according to claim 3 further comprising: a peripheral device-input/output controller means, said peripheral device-input/output controller means having a controller data bus of a first bit width and wherein said second synchronous bus has a second bit width different from said first bit width; a byte assembly register coupled between said second synchronous bus and said controller data bus for assembling data in bytes and words for exchange between said controller data bus and said second synchronous bus means.
Claim 16
Dependent Claim
38 words
The device controller according to claim 14 further comprising: a parity converting means coupled between said second synchronous bus and said controller bus for converting parity of data passed between said second synchronous bus and said controller bus.
Claim 17
Dependent Claim
171 words
The device controller according to claim 14 further comprising: multiplexer means coupled to said peripheral device-input/output controller means on one end and coupled to a first SCSI bus and to a second SCSI bus on the other end thereby to provide for connection to either said first SCSI bus or to said second SCSI bus through said device controller; third bus means coupled to said peripheral device-input/output control means; programmable interrupt logic means coupled between said third bus means and said first SCSI bus and said second SCSI bus to monitor preselected conditions on each of said first SCSI bus and said second SCSI bus; and second bus switch means coupled between said first bus means and said third bus means for passing command messages to said multiplexer means to select between said first SCSI bus and said second SCSI bus, to said programmable interrupt logic means for preselecting conditions which will cause an interrupt to said microprocessor means, and to said device-input/output controller means for controlling a selected SCSI bus.
Claim 18
Dependent Claim
51 words
The device controller according to claim 5 further comprising means coupled to said first bus means for communicating data between DCEs or DTEs via said second synchronous bus and said first port-input/output controller means or said second port-input/output controller means, including at least a universal receiver-transmitter and a synchronous communication controller.
Claim 19
Dependent Claim
83 words
The device controller according to claim 5 further including program means for handling Execute Input/Output Commands issued by each of said host processors, to said microprocessor means, said program means comprising: a peripheral port control driver means and port task means for controlling said first port-input/output controller means or said second port-input/output controller means; device task means in communication with said port task means; and device driver means for controlling peripheral devices coupled to said SCSI buses and to said first bus means.
Claim 20
Dependent Claim
224 words
A digital computer system, including at least a first host processor and a second host processor, a first input/output channel bus coupled to said first host processor, a second input/output channel bus coupled to said second host processor, an interprocessor bus, each of said host processors being coupled together by means of said interprocessor bus, said computer system comprising: a first device controller, said first device controller having a first port-input/output controller coupled to said first input/output channel bus and a second port-input/output controller coupled to said second input/output channel bus, a first peripheral device-input/output controller coupled to a first SCSI bus and a second peripheral device-input/output controller coupled to a second SCSI bus; and a second device controller, said second device controller having a third port-input/output controller coupled to said first input/output channel bus and a fourth port-input/output controller coupled to said second input/output channel bus, a third peripheral device-input/output controller coupled to said first SCSI bus and a fourth peripheral device-input/output controlIer coupled to said second SCSI bus; each said port-input/output controller having an ownership latch for granting ownership of each said device controller to multiple host processors and thereby providing at least four data paths between one of said first or second host processors and one of any peripheral devices coupled to said first SCSI bus or said second SCSI bus.
Claim 21
Dependent Claim
224 words
A digital computer system, including at least a first host processor and a second host processor, a first input/output channel bus coupled to said first host processor, a second input/output channel bus coupled to said second host processor, an interprocessor bus, each of said host processors being coupled together by means of said interprocessor bus, said computer system comprising: a first device controller, said first device controller having a first port-input/output controller coupled to said first input/output channel bus and a second port-input/output controller coupled to said second input/output channel bus, a first peripheral device-input/output controller coupled to a first SCSI bus and a second peripheral device-input/output controller coupled to a second SCSI bus; and a second device controller, said second device controller having a third port-input/output controller coupled to said first input/output channel bus and a fourth port-input/output controller coupled to said second input/output channel bus, a third peripheral device-input/output controller coupled to said first SCSI bus and a fourth peripheral device-input/output controlIer coupled to said second SCSI bus; each said port-input/output controller having an ownership latch for granting ownership of each said device controller to multiple host processors and thereby providing at least four data paths between one of said first or second host processors and one of any peripheral devices coupled to said first SCSI bus or said second SCSI bus.
Claim 22
Dependent Claim
150 words
The computer system according to claim 19 wherein each said device controller comprises: a first bus; a dedicated microprocessor having control over said first bus (the MPU bus); a second bus, said second bus operative at a different speed than said first bus; a multiple-channel direct memory access (DMA) controller means comprising a state machine, said DMA controller having control over said second bus (the data buffer bus) and control over and access to said first and second port-input/output controller for arbitrating access to said first bus; and a first bus switch coupled between said first bus and said second bus for communicating information on said first bus at a first speed to said second bus at a second speed and information on said second bus at said second speed to said first bus at said first speed under control of said DMA controller and upon request of said MPU.
Claim 23
Dependent Claim
104 words
For use in a digital computer system, a method for controlling data and command transfer in a device controller comprising: granting ownership of said device controller to a first host processor by means of a first ownership latch means of a first port input-output controller; and granting ownership of said device controller to a second host processor independently of said first port input/output controIler, by means of a second ownership latch means operative independently of said first ownership latch means thereby to provide multiple data paths between one of said first or second host processors and any peripheral devices coupled to said device controller.
Claim 24
Dependent Claim
104 words
For use in a digital computer system, a method for controlling data and command transfer in a device controller comprising: granting ownership of said device controller to a first host processor by means of a first ownership latch means of a first port input-output controller; and granting ownership of said device controller to a second host processor independently of said first port input/output controIler, by means of a second ownership latch means operative independently of said first ownership latch means thereby to provide multiple data paths between one of said first or second host processors and any peripheral devices coupled to said device controller.
Claim 25
Dependent Claim
75 words
The method according to claim 21 further including the steps of: defining by alternating time allocation a first channel and a second channel on a synchronous bus; and arbitrating time allocation between said first channel and said second channel, by means of a programmable state machine to regulate data transfer on said synchronous bus, and for allocating time on said synchronous bus to said microprocessor means at a lower priority than for said data transfer.
Claim 26
Dependent Claim
67 words
The method according to claim 23 further including the steps of: imposing a maximum latency between a data request and a data acknowledge issued by said state machine of no more than two bus cycles on any channel and wherein maximum latency between a bus request and a bus grant issued by said state machine is dependent upon load of said first channel and said second channel.
References Cited (Backward Citations)
No citation records indexed.
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