EP0287056A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Dynamic random access memory device having a plurality of one transistor type memory cells
Assignee: Micron Memory Japan Ltd
•
Filing: 1988-04-13
•
Granted: —
•
Expires: 2008-04-13
Abstract
Abstract A dynamic random access memory device having one transistor type memory cells is disclosed. The memory cell includes a trench type storage capacitor and a transfer gate transistor. The dielectric film of the capacitor is formed in the trench such that the upper part of the film above the upper wall of the trench adjacent to the major surface of the substrate is thicker than the other parts of the film in the trench.
Inventors
- 👤 Yasushi C/O Nec Corporation Okuyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:07
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
194 words
A dynamic random access memory device comprising a semiconductor substrate of one conductivity type and having a major surface, a transfer gate transistor formed on said major surface of said substrate and having source and drain regions of a conductivity type opposite to said substrate, a trench formed in said substrate from said major surface of said substrate into said substrate said trench having an upper wall adjacent to said major surface of said substrate and a lower wall adjacent to said upper wall continuously and including a bottom portion, an impurity layer of a conductivity type opposite to said substrate formed on said upper and lower walls of said trench and connected to one of said source and drain regions of said transistor, a dielectric film of a storage capacitor, said dielectric film including a first portion provided on said upper wall of said trench and a second portion provided on said lower wall of said trench, said first portion of said dielectric film being thicker than said second portion of said dielectric film, and a capacitor electrode continuously formed on said first and second portions of said dielectric film within said trench.
Claim 2
Dependent Claim
194 words
A dynamic random access memory device comprising a semiconductor substrate of one conductivity type and having a major surface, a transfer gate transistor formed on said major surface of said substrate and having source and drain regions of a conductivity type opposite to said substrate, a trench formed in said substrate from said major surface of said substrate into said substrate said trench having an upper wall adjacent to said major surface of said substrate and a lower wall adjacent to said upper wall continuously and including a bottom portion, an impurity layer of a conductivity type opposite to said substrate formed on said upper and lower walls of said trench and connected to one of said source and drain regions of said transistor, a dielectric film of a storage capacitor, said dielectric film including a first portion provided on said upper wall of said trench and a second portion provided on said lower wall of said trench, said first portion of said dielectric film being thicker than said second portion of said dielectric film, and a capacitor electrode continuously formed on said first and second portions of said dielectric film within said trench.
Claim 3
Dependent Claim
31 words
A memory device of Claim 1, in which the depth of said upper wall of said trench from said major surface of said substrate ranges from 0.5 µm to 2.0 µm.
Claim 4
Dependent Claim
79 words
A memory device of Claim 1, in which said dielectric film of said capacitor includes a first silicon oxide film on said upper and lower walls of said trench with a substantially uniform thickness and a silicon nitride film on the surface of said first silicon oxide film, the thickness of said silicon nitride film above said upper wall of said trench being larger than the thickness of said silicon nitride film above said lower wall of said trench.
Claim 5
Dependent Claim
97 words
A memory device of Claim 3, in which said dielectric film of said capacitor further includes a second silicon oxide film on the surface of said silicon nitride film above said upper and lower walls of said trench with a substantially uniform thickness, whereby said first portion of said dielectric film is constituted by said first silicon oxide film, said thick silicon nitride film and said second silicon oxide film, and said second portion of said dielectric film is constituted by said first silicon oxide film, said thin silicon nitride film and said second silicon oxide film
Claim 6
Dependent Claim
43 words
A memory device of Claim 3, in which said thickness of said silicon nitride film above said upper wall is 1.5 times or more and 3.0 times or less said thickness of said silicon nitride film above said lower wall of said trench.
Claim 7
Dependent Claim
30 words
A memory device of Claim 4, in which said first and second silicon oxide films are thermally grown films, and said silicon nitride film is a chemically vapour deposited film.
Claim 8
Dependent Claim
23 words
A memory device of Claim 4, in which the thickness of said second silicon oxide film ranges from 2 nm to 6 nm.
Claim 9
Dependent Claim
27 words
A memory device of Claim 1, in which said impurity layer is beforehand provided and is present when any voltage is not applied to said capacitor electrode.
Claim 10
Dependent Claim
22 words
A memory device of Claim 1, in which said impurity layer is produced when a voltage is applied to said capacitor electrode.
Claim 11
Dependent Claim
21 words
A memory device of Claim 1, in which said dielectric film is constituted only by a thermally grown silicon oxide film.
Claim 12
Dependent Claim
34 words
A memory device of Claim 1 further comprising an impurity region of said one conductivity type and having a higher impurity concentration than that of said substrate, said impurity region surrounding said impurity layer.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.