EP0285892A2
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EP
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Clock skew compensation system for pipeline processors
Assignee: Prime Computer Inc
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Filing: 1988-03-21
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Granted: —
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Expires: 2008-03-21
Abstract
Abstract A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.
Inventors
- 👤 Brian Lefsky
- 👤 Joseph L.Jr. Ardini
- 👤 Michael Schwartz
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 14:52
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3869
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
120 words
In a pipelined processor having multiple sequential stages including at least first and second stage register means each having means for receiving respective first and second clock signals for clocking information into each stage, means for accurately transferring information between stages in spite of skew between clock signals and including latch or holding means, and means coupling said latch means between said first and second stage register means, said latch means having means for receiving at least one of said first and second clock signals as a latching command, said latch means having one state in which information passes between stages, and another state for holding the information from said first stage register means for said second stage register means.
Claim 2
Dependent Claim
120 words
In a pipelined processor having multiple sequential stages including at least first and second stage register means each having means for receiving respective first and second clock signals for clocking information into each stage, means for accurately transferring information between stages in spite of skew between clock signals and including latch or holding means, and means coupling said latch means between said first and second stage register means, said latch means having means for receiving at least one of said first and second clock signals as a latching command, said latch means having one state in which information passes between stages, and another state for holding the information from said first stage register means for said second stage register means.
Claim 3
Independent Claim
130 words
A system for providing compensation for the skew of separate first and second clock signals used in a data processing system having multiple stages each including at least one register, said skew compensation system providing for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay, said skew compensation system comprising holding means, and means coupling said holding means between said first and second stage register means, said holding means having means for receiving at least one of said first and second clock signals as a hold command, said hold means having one state in which information passes between stages, as another state for holding the information from said first stage register means for said second stage register means.
Claim 4
Independent Claim
130 words
A system for providing compensation for the skew of separate first and second clock signals used in a data processing system having multiple stages each including at least one register, said skew compensation system providing for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay, said skew compensation system comprising holding means, and means coupling said holding means between said first and second stage register means, said holding means having means for receiving at least one of said first and second clock signals as a hold command, said hold means having one state in which information passes between stages, as another state for holding the information from said first stage register means for said second stage register means.
Claim 5
Dependent Claim
40 words
In a pipelined processor as set forth in claim 1 or 2 including combinatorial logic means and means coupling the combinatorial logic means in series circuit with the first and second stage register means and the latch or holding means.
Claim 6
Dependent Claim
37 words
In a pipelined processor as set forth in claim 3 wherein the latch or holding means has a data input coupled from the first stage register means and a data output coupled to the combinatorial logic means.
Claim 7
Dependent Claim
36 words
In a pipelined processor as set forth in claim 1 or 2 wherein the first stage register means includes a first register having a clock input and said latch or holding means has an enable input.
Claim 8
Dependent Claim
32 words
In a pipelined processor as set forth in claim 5 wherein said first clock signal couples in common to the first register clock input and the latch or holding means enable input.
Claim 9
Dependent Claim
25 words
In a pipelined processor as set forth in claim 6 wherein said latch or holding means enable input is a 1ow logic level enable input.
Claim 10
Dependent Claim
36 words
In a pipelined processor as set forth in claim 1 or 2 wherein the second stage register means includes a second register having a clock input and said latch or holding means has an enable input.
Claim 11
Dependent Claim
32 words
In a pipelined processor as set forth in claim 8 wherein said second clock signal couples in common to the second register clock input and the latch or holding means enable input.
Claim 12
Dependent Claim
25 words
In a pipelined processor as set forth in claim 9 wherein said latch or holding means enable input is a high logic level enable input.
Claim 13
Dependent Claim
72 words
In a pipelined processor as set forth in claim 1 or 2 wherein each said stage register means includes a data input D, a clock input C and a data output Q, wherein the register means Truth Table is as follows: wherein H = Logic High L = Logic Low X = Don't Change - = No Change L→ H = Low to High Transition H→ L = High to Low Transition
Claim 14
Dependent Claim
58 words
1n a pipelined processor as set forth in claim 1 or 2 wherein said latch or holding means includes a data input D, a clock input C, and a data output Q, wherein said latch means Truth Table is as follows: wherein H = Logic High L = Logic Low X = Don't Change - = No Change
Claim 15
Dependent Claim
58 words
In a pipelined processor as set forth in claim 1 or 2 wherein said latch or holding means include a data input D, a clock input C, and a data output Q, wherein said latch means Truth Table is as follows: wherein H = Logic High L = Logic Low X = Don't Change - = No Change
Claim 16
Independent Claim
114 words
A method of providing skew compensation between first and second clock signals used in a data-processing system in which there are multiple stages each including at least one register, said method providing for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay, the method comprising the steps of providing a holding means and coupling the holding means between the first and second registers, said holding means having means for receiving one of the clock signals, said holding means having one state in which information passes between stages, and another state for holding the information from the first register for the second register.
Claim 17
Independent Claim
114 words
A method of providing skew compensation between first and second clock signals used in a data-processing system in which there are multiple stages each including at least one register, said method providing for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay, the method comprising the steps of providing a holding means and coupling the holding means between the first and second registers, said holding means having means for receiving one of the clock signals, said holding means having one state in which information passes between stages, and another state for holding the information from the first register for the second register.
References Cited (Backward Citations)
No citation records indexed.
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