EP0285334A2
Expired / Lapsed
EP
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Universal asynchronous receiver-transmitter
Assignee: Advanced Micro Devices Inc
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Filing: 1988-03-25
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Granted: —
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Expires: 2008-03-25
Abstract
Abstract The UART can be selectably operated in a synchronous or an asynchronous mode. First-in, first-out (FIFO) registers (404,424) are provided for both the receiver and transmitter portions of the UART, and a parity error and special character recognizer unit (412) on the receive side flags characters when they are placed in the receive FIFO. Reception of a special character or one with a parity error is reported to the user via an interrupt mechanism (430). A random access memory (RAM)(413) with the special character recognizer stores user-supplied patterns which are recognized as special characters. User-accessible status and control registers (408) have bit positions which enable and control the enhanced functions of the UART while maintaining compatability with the industry standard.
Inventors
- 👤 Dale E. Gulick
- 👤 Terry G. Lawell
- 👤 Charles Crowe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 04:04
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/901; H04L49/9063; H04L49/9068; H04L49/9073; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04L69/00; H04L69/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
246 words
A universal asynchronous receiver-transmitter (UART)(54) connected to full-duplex means for low-speed serial receipt and transmission of data signals and having an internal bus, selectably operable in a synchronous mode, comprising: a source of asynchronous clock signals; receive clock multiplexer means (410) receiving a synchronous receive clock signal and said asynchronous clock signal and generating therefrom, in response to a receive synchronous/asynchronous mode selection, a receive clock signal; serial-to-parallel receive shift register (400) receiving serial data signals and said selectable clock signal generated by said receive clock MUX and generating parallel data signals; first-in, first-out (FIFO) receive register means (404) receiving in parallel said data signal generated by said receive shift register for storing a plurality of said parallel data signals and for generating in parallel at an output connects to said internal bus signals representing stored data received earliest in time; transmit clock multiplexer means (418) receiving said synchronous receive clock signals and said asynchronous clock signals and generating, in response to a transmit synchronous/asynchronous mode selection, a transmit clock signal; first-in, first-out (FIFO) transmit register means (424) receiving in parallel data signals on said internal bus, for storing a plurality of said received data signals received over time and for generating in parallel at a output signals representing said stored data received earliest in time; parallel-to-serial transmit shift register (420) receiving said selectable clock signal generated by said transmit clock MUX and said signals generated by said FIFO transmit register and generating serial data signals.
Claim 2
Dependent Claim
246 words
A universal asynchronous receiver-transmitter (UART)(54) connected to full-duplex means for low-speed serial receipt and transmission of data signals and having an internal bus, selectably operable in a synchronous mode, comprising: a source of asynchronous clock signals; receive clock multiplexer means (410) receiving a synchronous receive clock signal and said asynchronous clock signal and generating therefrom, in response to a receive synchronous/asynchronous mode selection, a receive clock signal; serial-to-parallel receive shift register (400) receiving serial data signals and said selectable clock signal generated by said receive clock MUX and generating parallel data signals; first-in, first-out (FIFO) receive register means (404) receiving in parallel said data signal generated by said receive shift register for storing a plurality of said parallel data signals and for generating in parallel at an output connects to said internal bus signals representing stored data received earliest in time; transmit clock multiplexer means (418) receiving said synchronous receive clock signals and said asynchronous clock signals and generating, in response to a transmit synchronous/asynchronous mode selection, a transmit clock signal; first-in, first-out (FIFO) transmit register means (424) receiving in parallel data signals on said internal bus, for storing a plurality of said received data signals received over time and for generating in parallel at a output signals representing said stored data received earliest in time; parallel-to-serial transmit shift register (420) receiving said selectable clock signal generated by said transmit clock MUX and said signals generated by said FIFO transmit register and generating serial data signals.
Claim 3
Dependent Claim
67 words
A UART according to claim 1, further including addressable means (413) for storing a plurality of "special" characters; and special character recognition means (412) connected to said receive shift register and said receive FIFO register means for determining if parallel data generated by said receive shift register corresponds to one of said "special" characters stored in said addressable means and for generating a signal indicating said determination.
Claim 4
Dependent Claim
72 words
A universal asynchronous receiver-transmitter (UART) according to claim 2 wherein said receive FIFO register means includes means (404) responsive to said special character determination signal for tagging each of said plurality of data stored therein as a special character and for generating a signal indicative of the presence of said tagged data upon receipt at said FIFO, and a signal indicative of the presence of said tagged data at said FIFO output.
Claim 5
Dependent Claim
140 words
A universal asynchronous receiver-transmitter (UART) according to claim 3 further including interface means connected to said internal bus for the connection of a microprocessor, and a plurality of register means (408) operably connected to said microprocessor interface each register means of said plurality comprising a plurality of bit storage locations, each said location for storing a predetermined status/control condition of said UART, wherein said plurality of status/control registers includes line Status Register means receiving said signal indicative of the presence of said tagged data upon receipt at said FIFO for setting a predetermined storage location therein according to said received signal, and wherein said plurality of status/control registers includes UART Status Register means receiving said signal indicative of the presence of said tagged data at said FIFO output for setting a predetermined storage location therein according to said received signal.
Claim 6
Dependent Claim
36 words
A UART according to claim 4 further including interrupt generating means (430) connected to said UART Status Register means for generating an interrupt signal indicative of said presence of said tagged data of said FIFO output.
Claim 7
Dependent Claim
62 words
A UART according to claim 5 wherein said interrupt generating means includes an Interrupt Identification Register means receive said signal indicative of said tagged data as said FIFO output for setting a plurality of predetermined ("Interrupt Source") storage locations therein according to said received signal, said Interrupt Identification Register means also having a predetermined ("Interrupt Pending") location indicating reception of said signal.
Claim 8
Dependent Claim
118 words
A UART according to claim 6 wherein said receive FIFO generates a signal indicative of the number of said data signals stored therein, and wherein said plurality of Control/Status Register means further includes UART Control Register means receiving Receive FIFO Threshold signals from said microprocessor interface for storing in predetermined storage locations therein said Receive FIFO Threshold signals, and wherein said Interrupt Identification Register means is responsive to said Receive FIFO Threshold signals stored in said UART Control Register and to said signal generated by said receive FIFO indicating the number of data signals stored therein and sets said plurality of Interrupt Source location therein indicating said Receive FIFO is storing greater than or equal to said Threshold.
Claim 9
Dependent Claim
112 words
A UART according to claim 7 wherein said transmit FIFO generates a signal indicative of the number of said data signals stored therein, and wherein said UART Control Rgister means further receives Transmit FIFO Threshold signals from said microprocessor interface further for storing in predetermined storage locations therein said Transmit FIFO Threshold signals, and wherein said Interrupt Identification Register means is responsive to said Transmit FIFO Threshold signals stored in said UART Control Register and said signal generated by said Transmit FIFO indicating the number of data signals stored therein and sets said plurality of Interrupt Source location therein indicating said Transmit FIFO is storing less than or equal to said Threshold.
Claim 10
Dependent Claim
42 words
A UART according to claim 3 further including means (412) connected to said receive shift register and said receive FIFO register means for testing the parity of parallel data generated by said receive shift register and for generating a parity error signal.
References Cited (Backward Citations)
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