EP0285158A2 — Frame synchronizing apparatus

Claim 1

Independent Claim 92 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said apparatus comprising: latching means (101) for converting said serial signals into parallel signals and for latching said parallel signals; and means for detecting a plural number of times of synchronization during the n bit interval in said one frame.

Claim 2

Dependent Claim 92 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said apparatus comprising: latching means (101) for converting said serial signals into parallel signals and for latching said parallel signals; and means for detecting a plural number of times of synchronization during the n bit interval in said one frame.

Claim 3

Dependent Claim 88 words

A frame synchronizing apparatus as set forth in claim 1, wherein said means for detecting a plural number of times of synchronization comprises: synchronization detecting means (102) for detecting said frame synchronizing signal from said parallel signals latched in said latching means, and latch timing signal generating means (103) for generating a plural number of times of latch timing pulses during said n bit interval in said one frame, said plural number of times being smaller than n, said latch timing pulses being applied to said latching means.

Claim 4

Dependent Claim 101 words

A frame synchronizing apparatus as set forth in claim 1, wherein said means for detecting a plural number of times of synchronizations comprises: a predetermined number smaller than n of a synchronization detecting means (102) for detecting said frame synchronizing signal by extracting said parallel signals latched respectively in different positions in said latching means, and latch timing signal generating means (103) for generating a plural number of times of latch timing pulses during said n bit interval in said one frame, said plural number of times being smaller than n, said latch timing pulses being applied to said latching means.

Claim 5

Dependent Claim 73 words

A frame synchronizing apparatus as set forth in claim 1, wherein said means for detecting a plural number of times of synchronization comprises: a predetermined number equal to n of a synchronization detecting means (102) for detecting said frame synchronizing signal by extracting said parallel signals latched respectively in different positions in said latching means, and latch timing signal generating means (103) for generating a latch timing pulse applied to said latching means.

Claim 6

Dependent Claim 144 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal collectively arranged in one frame, said apparatus comprising: latching means (101) for converting said serial signals into parallel signals and for latching said parallel signals; synchronization detecting means (102) for detecting said frame synchronizing signal from said parallel signals latched in said latching means, and latch timing signal generating means (103) for providing, for said latching means (101), a latch timing pulse having a frequency of f₀/k Hz, where n > k ≧ 2, before the detection of said frame synchronizing signal and having a frequency of f₀/n Hz after the detection of said frame synchronizing signal.

Claim 7

Dependent Claim 144 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal collectively arranged in one frame, said apparatus comprising: latching means (101) for converting said serial signals into parallel signals and for latching said parallel signals; synchronization detecting means (102) for detecting said frame synchronizing signal from said parallel signals latched in said latching means, and latch timing signal generating means (103) for providing, for said latching means (101), a latch timing pulse having a frequency of f₀/k Hz, where n > k ≧ 2, before the detection of said frame synchronizing signal and having a frequency of f₀/n Hz after the detection of said frame synchronizing signal.

Claim 8

Dependent Claim 48 words

A frame synchronizing apparatus as set forth in claim 5, wherein said latch timing signal generating means (103) comprises a variable output counter (11) for varying the frequency of said latch timing pulse (f₀/k, f₀/n) in accordance with a detection by said synchronization detecting means of a synchronization.

Claim 9

Dependent Claim 156 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the same synchronizing signal collectively arranged in one frame, said apparatus comprising: latching means (101) for converting said serial signals into parallel signals and for latching said parallel signals; parallel synchronization detecting means (102A) having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of said latched signal to detect said frame synchronizing signal; and latch timing signal generating means (103) for providing, for said latching means (101), a latch timing pulse having frequency of f₀/k Hz, where n > k ≧ 2, before the detection of said frame synchronizing signal and having a frequency of f₀/n Hz after the detection of said frame synchronizing signal.

Claim 10

Dependent Claim 156 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the same synchronizing signal collectively arranged in one frame, said apparatus comprising: latching means (101) for converting said serial signals into parallel signals and for latching said parallel signals; parallel synchronization detecting means (102A) having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of said latched signal to detect said frame synchronizing signal; and latch timing signal generating means (103) for providing, for said latching means (101), a latch timing pulse having frequency of f₀/k Hz, where n > k ≧ 2, before the detection of said frame synchronizing signal and having a frequency of f₀/n Hz after the detection of said frame synchronizing signal.

Claim 11

Dependent Claim 49 words

A frame synchronizing apparatus as set forth in claim 7, further comprising: output selection means (104) for extracting from said latched signals, a signal of one time slot at a position corresponding to the synchronization detecting portion which has detected said frame synchronizing signal and outputting said extracted signal.

Claim 12

Dependent Claim 54 words

A frame synchronizing apparatus as set forth in claim 8, wherein said output selection means (104) is a selector means for selecting a signal in one time slot from a plurality of output lines of said latching means (101) under the control of the synchronization detecting portion which has detected said frame synchronizing signal.

Claim 13

Dependent Claim 109 words

A frame synchronizing apparatus as set forth in claim 7, wherein said latch timing generating means comprises a variable output counter (11) for varying the frequency of said latch timing pulse (f₀/k, f₀/n) in accordance with a detection by said synchronization detecting means of a synchronization said parallel synchronization detecting means comprising plural stages of synchronization detecting portions (#1 - #k), a synchronization control portion (13) and a synchronization protection portion (9), whereby when a synchronization is detected in one of the outputs of said plural stages of synchronous detecting portions, said synchronization protection portion outputs a mode selecting signal for selecting the mode of said variable output counter.

Claim 14

Dependent Claim 53 words

A frame synchronizing apparatus as set forth in claim 7, wherein said output selection means (104) is a phase selection means for changing the phase of a latch timing pulse in said latch timing signal generating means (103) under the control of the synchronization detecting portion which has detected said frame synchronous signal.

Claim 15

Dependent Claim 87 words

A frame synchronizing apparatus as set forth in claim 7, wherein said variable output counter comprises: a counter for generating two types of clocks (f₀/k and f₀/n) counters, phase selecting means for selecting one of k clocks output from one of said two counters for generating a timing of a unit of said frame, and a memory for storing the number of said synchronization detecting portion when said synchronization detecting portion detects a synchronization, whereby, the phase of the timing (f₀/n) is changed by the stored number.

Claim 16

Dependent Claim 25 words

A synchronization apparatus as set forth in claim 7, further comprising a synchronization control portion for changing the clock (f₀/n) from said variable output counter.

Claim 17

Dependent Claim 108 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said apparatus comprising: latching means (101B) for converting said serial signals into parallel signals and for latching (2n-1) bits of said parallel signals; and parallel synchronization detecting means (102B) having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of said latched signal to detect said frame synchronizing signal.

Claim 18

Dependent Claim 108 words

A frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication, said digital signals consisting of serial signals at a rate of f₀ (bps), said serial signals including a frame synchronizing signal constituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said apparatus comprising: latching means (101B) for converting said serial signals into parallel signals and for latching (2n-1) bits of said parallel signals; and parallel synchronization detecting means (102B) having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of said latched signal to detect said frame synchronizing signal.

Claim 19

Dependent Claim 49 words

A frame synchronizing apparatus as set forth in claim 14, further comprising: output selection means (104B) for extracting, from said latched signals, a signal of one time slot at a position corresponding to the synchronization detecting portion which has detected said frame synchronizing signal and outputting said extracted signal.

Claim 20

Dependent Claim 52 words

A frame synchronizing apparatus as set forth in claim 15, wherein said output selection means is selector means for selecting a signal in one time slot out of a plurality of output lines of said latching means under the control of the synchronization detecting portion which has detected said frame synchronizing signal.

Claim 21

Dependent Claim 74 words

A frame synchronizing apparatus as set forth in claim 15, wherein said parallel synchronization detecting means comprises (2n-1) stages of synchronization detecting portions (#1 - #k), a synchronization control portion (13a) and a synchronization protection portion (9), whereby when a synchronization is detected in one of the outputs of said plural stages of synchronous detecting portions, said synchronization protection portion outputs a mode selecting signal for selecting the mode of said variable output counter.

Claim 22

Dependent Claim 45 words

A frame synchronizing apparatus as set forth in claim 14, wherein said output selection means (104B) is clock phase selection means for changing latch timing in said latching means (101B) under the control of the synchronization detecting portion which has detected said frame synchronous signal.

Claim 23

Dependent Claim 68 words

A frame synchronizing apparatus as set forth in claim 14, wherein said latching means comprises two latching portions each for storing n bits, said two latching portions alternatively latching input signals in response to a clock signal having a frequency of f₀/2n, said apparatus further comprising selecting means for selecting the outputs of said latching means to output (2n-1) bits of information to said parallel synchronization detecting means.

Claim 24

Dependent Claim 76 words

A frame synchronizing apparatus as set forth in claim 14, further comprising a timing signal generating circuit having an output counter with n kinds of phases, for providing a timing signal to said latching means, one of said phases being selected in response to the output of the detecting portion in said parallel synchronization detecting means that has detected the synchronization, whereby said latching means latches said parallel signals at the timing of said selected phases.

Claim 25

Dependent Claim 84 words

A frame synchronizing apparatus as set forth in claim 14, further comprising a timing signal generating circuit having a counter (3) for providing a timing signal to said latching means, said parallel synchronization detecting means comprising a synchronization control portion (13a) and a shift pulse generating portion (16) controlled by said synchronization control portion (13a), said timing signal being supplied to said latching means by shifting the count value of said counter in response to the pulse from said shift pulse generating portion (16).

Claim 26

Dependent Claim 62 words

A frame synchronizing apparatus as set forth in claim 21, wherein said latching means comprises two latching portions (2A, 2B) alternatively latching input signals in response to a clock signal having a frequency of fo/2n, said apparatus further comprising selecting means (2C) for selecting the outputs of said latching means to output (2n-1) bits of information to said parallel synchronization detecting means.

Frame synchronizing apparatus

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