High speed computer system

Claim 2

A high speed computer system characterised by comprising: a plurality of memory means (1,2,3) for storing instructions, each memory means being arranged to store instructions belonging to the same category; a plurality of processors (5,9,10) connected to a respective one of said memory means for executing instructions, each processor having a configuration so as, in operation, to execute instructions stored in said memory means connected thereto and a program counter for designating a memory address under which an instruction to be executed is stored, said program counter including means for counting up the count value; data memory means (7) connected to one of said processors for storing data used in execution of instructions; and communication line means (12) interconnecting said processors for synchronising execution of each processor.

Claim 3

A high speed computer system as claimed in claim 1 characterised in that same plurality of memory means (1,2,3) comprises a transfer instruction memory (1) for storing data transfer operation instructions, an arithmetic instruction memory (2) for storing arithmetic operation instructions and a branch instruction memory (3) for storing branch operation instructions.

Claim 4

A high speed computer system as claimed in claim 2 characterised in that said plurality of processors comprise a transfer processor (5) connected to said transfer instruction memory (1) for executing data transfer operation instructions, an arithmetic operation processor (9) connected to said arithmetic instruction memory (2) for executing arithmetic operation instructions and a branch processor (10) connected to said branch instruction memory (3) for executing branch operation instructions.

Claim 5

A high speed computer system as claimed in any preceding claim characterised by register means (8) connected to at least one of said processors for storing data temporarily.

Claim 6

A high speed computer system as claimed in claim 4 when dependent upon claim 3 characterised in that said register means (8) is connected to said transfer processor (5) and to said arithmetic operation processor (9), said transfer processor, in operation, transferring data between said data memory (1) and said register means (8) and said arithmetic operation processor, in operation, performing arithmetic operations on data stored in said register means.

Claim 7

A high speed computer system as claimed in claim 3, 4 or 5 characterised in that said branch processor (10) has output means (11) for outputting branching addresses to one or more other processors (5,9) according to destination.

Claim 8

A high speed computer system as claimed in any preceding claim including prefetch means (13,14) connected between each of said memory means (1,2,3) and its respective processor (5,9,10) for prefetching instructions from said memory means.

Claim 9

A high speed computer system as claimed in claim 7 characterised in that said prefetch means includes fetcher means (13) for fetching a plurality of instructions parallely and further register means (14) for storing fetched instructions, said fetcher means having counter means for designating starting memory addresses in order to fetch a plurality of instructions stored in said memory means.

Claim 10

A high speed computer system for execution of instruction flow under control of program counters comprising: a plurality of memory means for storing instructions; each memory means storing instructions belonging to same category; a plurality of processors connected one to one to said plurality of memory means for executing instructions; each processor having a simplified configuration so as to execute instructions stored in said memory means connected to the processor high speed and a program counter for designating a memory address under which an instruction to be executed is stored, said program counter including means for counting up the count value; data memory means connected to one of said processors for storing data used in execution of instructions; and communication lines interconnecting said processors for synchronising execution of each processors.

Claim 11

A high speed computer system for execution of instruction flow under control of program counters comprising: a plurality of memory means for storing instructions; each memory means storing instructions belonging to same category; a plurality of processors connected one to one to said plurality of memory means for executing instructions; each processor having a simplified configuration so as to execute instructions stored in said memory means connected to the processor high speed and a program counter for designating a memory address under which an instruction to be executed is stored, said program counter including means for counting up the count value; data memory means connected to one of said processors for storing data used in execution of instructions; and communication lines interconnecting said processors for synchronising execution of each processors.