Selective power gating

Claim 2

A selective power gating device for providing power from a power supply to an electrical device adapted to receive at least two levels of power, comprising: detection means coupled to the electrical device for determining a selected portion of the electrical device requiring a higher level of power; and power gating means coupled to the detection means, electrical device and the power supply means for supplying the higher level of power to the selected portion and a lower level of power to a remaining portion; whereby overall power consumption of the electrical device is reduced.

Claim 3

A selective power gating device for providing power from a power supply means to a memory device, the memory device being coupleable to an external device for reading or writing, comprising: the memory device including at least two blocks, each block including control circuitry and memory circuitry, each block being adapted to receive power at each of at least two levels of power, a higher active level and a lower retention level required to maintain data in a block; means for applying the lower retention level of power to all of the blocks; detection means coupled to the external device for identifying a selected block of the memory device requiring a higher level of power; and power gating means coupled to the detection means and the power supply means for normally preventing the supply of the higher active level of power to the blocks and selectively supplying the higher level of power to the identified block when required for operation of the block of the memory device; whereby each of the at least two of the blocks is normally powered at the lower retention level of power except when the higher active level of power is required so that overall power consumption of the memory device is reduced.

Claim 4

A selective power gating device for providing power from a power supply means to a memory device, the memory device being coupleable to an external device for reading or writing, comprising: the memory device including at least two blocks, each block including control circuitry and memory circuitry, each block being adapted to receive power at each of at least two levels of power, a higher active level and a lower retention level required to maintain data in a block; means for applying the lower retention level of power to all of the blocks; detection means coupled to the external device for identifying a selected block of the memory device requiring a higher level of power; and power gating means coupled to the detection means and the power supply means for normally preventing the supply of the higher active level of power to the blocks and selectively supplying the higher level of power to the identified block when required for operation of the block of the memory device; whereby each of the at least two of the blocks is normally powered at the lower retention level of power except when the higher active level of power is required so that overall power consumption of the memory device is reduced.

Claim 5

A selective power gating computer system, comprising: memory means for storing information, said memory means having at least two memory portions, each of which is adapted to separately receive two different power levels, a higher operating power level and a lower data retention power level required to maintain the integrity of the data in the memory portion; processing means coupled to the memory means for controlling data processing and the movement of data at least one of to and from the memory means; power supply means adapted to supply power at the higher operating power level and the lower data retention power level to the memory means; detection means coupled to the processing means for identifying a selected memory portion of the memory means requiring the higher operating power level; and power gating means coupled to the power supply means, detection means and memory means for normally preventing the supply of the higher operating power level to the memory portions while not preventing the supply of the lower retention level of power to those of the at least two memory portions not identified by the detection means, and selectively supplying the higher operating power level to the identified selected memory portion of the memory means when required for operation of the selected memory portion; whereby the power consumption of the memory means is reduced.

Claim 6

A selective power gating computer system, comprising: memory means for storing information, said memory means having at least two memory portions, each of which is adapted to separately receive two different power levels, a higher operating power level and a lower data retention power level required to maintain the integrity of the data in the memory portion; processing means coupled to the memory means for controlling data processing and the movement of data at least one of to and from the memory means; power supply means adapted to supply power at the higher operating power level and the lower data retention power level to the memory means; detection means coupled to the processing means for identifying a selected memory portion of the memory means requiring the higher operating power level; and power gating means coupled to the power supply means, detection means and memory means for normally preventing the supply of the higher operating power level to the memory portions while not preventing the supply of the lower retention level of power to those of the at least two memory portions not identified by the detection means, and selectively supplying the higher operating power level to the identified selected memory portion of the memory means when required for operation of the selected memory portion; whereby the power consumption of the memory means is reduced.

Claim 7

A selective power gating device for providing power from a power supply means to a memory device, the memory device being coupleable to an external device for reading or writing, comprising: the memory device including at least two blocks, each block including control circuitry and memory circuitry, the memory circuitry for each block being adapted to receive each of at least two levels of power, a higher active level and a lower retention level required to maintain data in a block; means for applying the lower retention level of power to the memory circuitry of all of the blocks; detection means coupled to the external device for identifying a selected block of the memory device requiring the higher active level of power; and power gating means coupled to the detection means and the power supply means for normally preventing the supply of the higher active level of power to memory circuitry of the blocks while not preventing the supply of the lower retention level of power to at least the memory circuitry of the at least two blocks not identified by the detection means, and selectively supplying the higher active level of power to the memory circuitry of the identified selected block; whereby each of the at least two blocks has its memory circuitry powered at the lower retention level of power except when the higher active level of power is required so that overall power consumption of the memory device is reduced.

Claim 8

A selective power gating device for providing power from a power supply means to a memory device, the memory device being coupleable to an external device for reading or writing, comprising: the memory device including at least two blocks, each block including control circuitry and memory circuitry, the memory circuitry for each block being adapted to receive each of at least two levels of power, a higher active level and a lower retention level required to maintain data in a block; means for applying the lower retention level of power to the memory circuitry of all of the blocks; detection means coupled to the external device for identifying a selected block of the memory device requiring the higher active level of power; and power gating means coupled to the detection means and the power supply means for normally preventing the supply of the higher active level of power to memory circuitry of the blocks while not preventing the supply of the lower retention level of power to at least the memory circuitry of the at least two blocks not identified by the detection means, and selectively supplying the higher active level of power to the memory circuitry of the identified selected block; whereby each of the at least two blocks has its memory circuitry powered at the lower retention level of power except when the higher active level of power is required so that overall power consumption of the memory device is reduced.

Claim 9

A selective power gating device for providing power from a power supply means to a memory device, the memory device being coupleable to an external device for reading or writing, comprising: the memory device including at least two blocks, each block including control circuitry and memory circuitry, the con­trol and memory circuitry for each block being adapted to receive at least two levels of power, a higher active level and a lower level, said lower level being either a no power level or a retention level of power required to maintain data in a block; detection means coupled to the external device for identifying from the output of the external device a selected block of the memory device requiring the higher active level of power; and power gating means coupled to the detection means and the power supply means for normally preventing the supply of the higher active level of power to the control and memory circuitry of the blocks while not preventing the supply of a lower retention level of power to at least the memory circuitry of the at least two blocks not identified by the detection means, and selectively supplying the higher active level of power to the control and memory circuitry of the identified block; whereby the control and memory circuitry of each of the two blocks is powered to the active level of power only when required so that overall power consumption of the memory device is reduced.

Claim 10

A selective power gating device for providing power from a power supply means to a memory device, the memory device being coupleable to an external device for reading or writing, comprising: the memory device including at least two blocks, each block including control circuitry and memory circuitry, the con­trol and memory circuitry for each block being adapted to receive at least two levels of power, a higher active level and a lower level, said lower level being either a no power level or a retention level of power required to maintain data in a block; detection means coupled to the external device for identifying from the output of the external device a selected block of the memory device requiring the higher active level of power; and power gating means coupled to the detection means and the power supply means for normally preventing the supply of the higher active level of power to the control and memory circuitry of the blocks while not preventing the supply of a lower retention level of power to at least the memory circuitry of the at least two blocks not identified by the detection means, and selectively supplying the higher active level of power to the control and memory circuitry of the identified block; whereby the control and memory circuitry of each of the two blocks is powered to the active level of power only when required so that overall power consumption of the memory device is reduced.

Claim 11

The selective power gating device of claim 5, wherein the higher level of power corresponds to operating power required for at least one of reading from or writing to the memory device.

Claim 12

The selective power dating device of claim 5, wherein the detection means includes an address decoder coupled to the external device to receive addresses associated with each block which identify the block requiring the higher active level of power.

Claim 13

The selective power gating device of claim 5, wherein the detection means includes a programmable array logic device coupled to the external device to receive addresses associated with each block which identify the block requiring the higher active level of power.

Claim 14

The selective power gating device of claim 5, further including delay means for delaying the memory device from receiv­ing a read or write instruction until the power gating means supplies the higher level of power to the selected block.