Structure of complementary field effect transistor

Claim 2

A complementary field effect transistor fabricated in a semiconductor substrate of a first conductivity type, comprising: a) a well formed in a surface portion of said semiconductor substrate and having a second conductivity type opposite to said first conductivity type, a groove being defined by a first side wall of the surface portion of said semiconductor substrate, a first bottom wall of the surface portion, a second side wall of said well and a second bottom wall of the well; b) a first drain region of said second conductivity type formed in said semiconductor substrate and exposed to said first bottom wall; c) a first source region of said second conductivity type formed in said surface portion and spaced apart from said first drain region; d) a first gate insulating film formed on said first side wall; e) a first gate electrode formed on said first gate insulating film and operative to cause a channel to take place between said first drain region and said first source region, said first drain region, said first source region, said first gate insulating film and said first gate electrode forming in combination a first MIS type field effect transistor; f) a second drain region of said first conductivity type formed in said well and exposed to said second bottom wall; g) a second source region of said first conductivity type formed in a surface portion of said well and spaced apart from said first drain region; h) a second gate insulating film formed on said first side wall; i) a second gate electrode formed on said second gate insulating film and operative to cause a channel to take place between said second drain region and said second source region, said second drain region, said second source region, said second gate insulating film and said second gate electrode forming in combination a second MIS type field effect transistor; j) a conductive material provided in said groove and electrically interconnecting said first region and said second drain region to form said complementary field effect transistor; and k) an insulating wall region formed between said first drain region and said second drain region.

Claim 3

A complementary field effect transistor as set forth in claim 1, in which said first source region is electrically connected to a first constant voltage source.

Claim 4

A complementary field effect transistor as set forth in claim 1, in which said second source region is electrically connected to a second constant voltage source.

Claim 5

A complementary field effect transistor as set forth in claim 1, in which said semiconductor substrate is formed of single crystal silicon.

Claim 6

A complementary field effect transistor as set forth in claim 1, in which said first and second gate electrodes are formed of polycrystalline silicon.

Claim 7

A complementary field effect transistor as set forth in claim 1, in which said first and second gate insulating films are formed of silicon dioxide.

Claim 8

A complementary field effect transistor as set forth in claim 1, in which said insulating wall region is formed of silicon dioxide.

Claim 9

A complementary field effect transistor as set forth in claim 1, in which said insulating wall region has a bottom portion deeper than a bottom portion of said well.

Claim 10

A flip-flop circuit fabricated in a semiconductor substrate of a first conductivity type, comprising: a) a well formed in a surface portion of said semiconductor substrate and having a second conductivity type opposite to said first conductivity type, a first groove being defined by a first side wall of the surface portion of said semiconductor substrate, a first bottom wall of the surface portion, a second side wall of said well and a second bottom wall of the well, a second groove being separated from said first groove and defined by a third side wall of the surface portion of said semiconductor substrate, a third bottom wall of the surface portion, a fourth side wall of said well and a fourth bottom wall of the well; b) a first drain region of said second conductivity type formed in said semiconductor substrate and exposed to said first bottom wall; c) a first source region of said second conductivity type formed in said surface portion and spaced apart from said first drain region; d) a first gate insulating film formed on said first side wall; e) a first gate electrode formed on said first gate insulating film and operative to cause a channel to take place between said first drain region and said first source region, said first drain region, said first source region, said first gate insulating film and said first gate electrode forming in combination a first MIS type field effect transistor; f) a second drain region of said first conductivity type formed in said well and exposed to said second bottom wall; g) a second source region of said first conductivity type formed in a surface portion of said well and spaced apart from said first drain region; h) a second gate insulating film formed on said second side wall; i) a second gate electrode formed on said second gate insulating film and operative to cause a channel to take place between said second drain region and said second source region, said second drain region, said second source region, said second gate insulating film and said second gate electrode forming in combination a second MIS type field effect transistor; j) a first conductive material provided in said first groove and electrically interconnecting said drain region and said second drain region to form a first complementary field effect transistor; k) a third drain region of said second conductivity type formed in said semiconductor substrate and exposed to said third bottom wall; l) a third source region of said second conductivity type formed in said surface portion and spaced apart from said third drain region; m) a third gate insulating film formed on said third side wall; n) a third gate electrode formed on said third gate insulating film and operative to cause a channel to take place between said third drain region and said third source region, said third drain region, said third source region, said third gate insulating film and said third gate electrode forming in combination a third MIS type field effect transistor; o) a fourth drain region of said first conductivity type formed in said well and exposed to said fourth bottom wall; p) a fourth source region of said first conductivity type formed in the surface portion of said well and spaced apart from said fourth drain region; q) a fourth gate insulating film formed on said fourth side wall; r) a fourth gate electrode formed on said fourth gate insulating film and operative to cause a channel to take place between said fourth drain region and said fourth source region, said fourth drain region, said fourth source region, said fourth gate insulating film and said fourth gate electrode forming in combination a fourth MIS type field effect transistor; s) a second conductive material provided in said second groove and electrically interconnecting said third drain region and said fourth drain region to form a second complementary field effect transistor; and t) an insulating wall region formed between said first and second drain regions and between said third and fourth drain regions, wherein said first conductive material is coupled to said third and fourth gate electrodes, and wherein said second conductive material is coupled to said first and second gate electrodes.

Claim 11

A flip-flop circuit fabricated in a semiconductor substrate of a first conductivity type, comprising: a) a well formed in a surface portion of said semiconductor substrate and having a second conductivity type opposite to said first conductivity type, a first groove being defined by a first side wall of the surface portion of said semiconductor substrate, a first bottom wall of the surface portion, a second side wall of said well and a second bottom wall of the well, a second groove being separated from said first groove and defined by a third side wall of the surface portion of said semiconductor substrate, a third bottom wall of the surface portion, a fourth side wall of said well and a fourth bottom wall of the well; b) a first drain region of said second conductivity type formed in said semiconductor substrate and exposed to said first bottom wall; c) a first source region of said second conductivity type formed in said surface portion and spaced apart from said first drain region; d) a first gate insulating film formed on said first side wall; e) a first gate electrode formed on said first gate insulating film and operative to cause a channel to take place between said first drain region and said first source region, said first drain region, said first source region, said first gate insulating film and said first gate electrode forming in combination a first MIS type field effect transistor; f) a second drain region of said first conductivity type formed in said well and exposed to said second bottom wall; g) a second source region of said first conductivity type formed in a surface portion of said well and spaced apart from said first drain region; h) a second gate insulating film formed on said second side wall; i) a second gate electrode formed on said second gate insulating film and operative to cause a channel to take place between said second drain region and said second source region, said second drain region, said second source region, said second gate insulating film and said second gate electrode forming in combination a second MIS type field effect transistor; j) a first conductive material provided in said first groove and electrically interconnecting said drain region and said second drain region to form a first complementary field effect transistor; k) a third drain region of said second conductivity type formed in said semiconductor substrate and exposed to said third bottom wall; l) a third source region of said second conductivity type formed in said surface portion and spaced apart from said third drain region; m) a third gate insulating film formed on said third side wall; n) a third gate electrode formed on said third gate insulating film and operative to cause a channel to take place between said third drain region and said third source region, said third drain region, said third source region, said third gate insulating film and said third gate electrode forming in combination a third MIS type field effect transistor; o) a fourth drain region of said first conductivity type formed in said well and exposed to said fourth bottom wall; p) a fourth source region of said first conductivity type formed in the surface portion of said well and spaced apart from said fourth drain region; q) a fourth gate insulating film formed on said fourth side wall; r) a fourth gate electrode formed on said fourth gate insulating film and operative to cause a channel to take place between said fourth drain region and said fourth source region, said fourth drain region, said fourth source region, said fourth gate insulating film and said fourth gate electrode forming in combination a fourth MIS type field effect transistor; s) a second conductive material provided in said second groove and electrically interconnecting said third drain region and said fourth drain region to form a second complementary field effect transistor; and t) an insulating wall region formed between said first and second drain regions and between said third and fourth drain regions, wherein said first conductive material is coupled to said third and fourth gate electrodes, and wherein said second conductive material is coupled to said first and second gate electrodes.

Claim 12

A static type random access memory cell fabricated on a semiconductor substrate of a first conductivity type, comprising: a) a well formed in a surface portion of said semiconductor substrate and having a second conductivity type opposite to said first conductivity type, a first groove being defined by a first side wall of the surface portion of said semiconductor substrate, a first bottom wall of the surface portion, a second side wall of said well and a second bottom wall of the well, a second groove being separated from said first groove and defined by a third side wall of the surface portion of said semiconductor substrate, a third bottom wall of the surface portion, a fourth side wall of said well and a fourth bottom wall of the well; b) a first drain region of said second conductivity type formed in said semiconductor substrate and exposed to said first bottom wall; c) a first source region of said second conductivity type formed in said surface portion and spaced apart from said first drain region; d) a first gate insulating film formed on said first side wall; e) a first gate electrode formed on said first gate insulating film and operative to cause a channel to take place between said first drain region and said first source region, said first drain region, said first source region, said first gate insulating film and said first gate electrode forming in combination a first MIS type field effect transistor; f) a second drain region of said first conductivity type formed in said well and exposed to said second bottom wall; g) a second source region of said first conductivity type formed in a surface portion of said well and spaced apart from said first drain region; h) a second gate insulating film formed on said second side wall; i) a second gate electrode formed on said second gate insulating film and operative to cause a channel to take place between said second drain region and said second source region, said second drain region, said second source region, said second gate insulating film and said second gate electrode forming in combination a second MIS type field effect transistor; j) a first conductive material provided in said first groove and electrically interconnecting said first drain region and said second drain region to form a first complementary field effect transistor; k) a third drain region of said second conductivity type formed in said semiconductor substrate and exposed to said third bottom wall; l) a third source region of said second conductivity type formed in said surface portion and spaced apart from said third drain region; m) a third gate insulating film formed on said third side wall; n) a third gate electrode formed on said third gate insulating film and operative to cause a channel to take place between said third drain region and said third source region, said third drain region, said third source region, said third gate insulating film and said third gate electrode forming in combination a third MIS type field effect transistor; o) a fourth drain region of said first conductivity type formed in said well and exposed to said fourth bottom wall; p) a fourth source region of said first conductivity type formed in the surface portion of said well and spaced apart from said fourth drain region; q) a fourth gate insulating film formed on said fourth side wall; r) a fourth gate electrode formed on said fourth gate insulating film and operative to cause a channel to take place between said fourth drain region and said fourth source region, said fourth drain region, said fourth source region, said fourth gate insulating film and said fourth gate electrode forming in combination a fourth MIS type field effect transistor; s) a second conductive material provided in said second groove and electrically interconnecting said third drain region and said fourth drain region to form a second complementary field effect transistor, said first and second conductive material being coupled to said third and fourth gate electrodes and to said first and second gate electrodes, respectively to form a flip-­flop circuit; t) an insulating wall region formed between said first and second drain regions and between said third and fourth drain regions; u) a first switching transistor having a first control gate coupled to a word line and capable of providing a conduction path between a first bit line and said first conductive material; and v) a second switching transistor having a second control gate coupled to said word line and capable of providing a conduction path between a second bit line and said second conductive material.

Claim 13

A static type random access memory cell fabricated on a semiconductor substrate of a first conductivity type, comprising: a) a well formed in a surface portion of said semiconductor substrate and having a second conductivity type opposite to said first conductivity type, a first groove being defined by a first side wall of the surface portion of said semiconductor substrate, a first bottom wall of the surface portion, a second side wall of said well and a second bottom wall of the well, a second groove being separated from said first groove and defined by a third side wall of the surface portion of said semiconductor substrate, a third bottom wall of the surface portion, a fourth side wall of said well and a fourth bottom wall of the well; b) a first drain region of said second conductivity type formed in said semiconductor substrate and exposed to said first bottom wall; c) a first source region of said second conductivity type formed in said surface portion and spaced apart from said first drain region; d) a first gate insulating film formed on said first side wall; e) a first gate electrode formed on said first gate insulating film and operative to cause a channel to take place between said first drain region and said first source region, said first drain region, said first source region, said first gate insulating film and said first gate electrode forming in combination a first MIS type field effect transistor; f) a second drain region of said first conductivity type formed in said well and exposed to said second bottom wall; g) a second source region of said first conductivity type formed in a surface portion of said well and spaced apart from said first drain region; h) a second gate insulating film formed on said second side wall; i) a second gate electrode formed on said second gate insulating film and operative to cause a channel to take place between said second drain region and said second source region, said second drain region, said second source region, said second gate insulating film and said second gate electrode forming in combination a second MIS type field effect transistor; j) a first conductive material provided in said first groove and electrically interconnecting said first drain region and said second drain region to form a first complementary field effect transistor; k) a third drain region of said second conductivity type formed in said semiconductor substrate and exposed to said third bottom wall; l) a third source region of said second conductivity type formed in said surface portion and spaced apart from said third drain region; m) a third gate insulating film formed on said third side wall; n) a third gate electrode formed on said third gate insulating film and operative to cause a channel to take place between said third drain region and said third source region, said third drain region, said third source region, said third gate insulating film and said third gate electrode forming in combination a third MIS type field effect transistor; o) a fourth drain region of said first conductivity type formed in said well and exposed to said fourth bottom wall; p) a fourth source region of said first conductivity type formed in the surface portion of said well and spaced apart from said fourth drain region; q) a fourth gate insulating film formed on said fourth side wall; r) a fourth gate electrode formed on said fourth gate insulating film and operative to cause a channel to take place between said fourth drain region and said fourth source region, said fourth drain region, said fourth source region, said fourth gate insulating film and said fourth gate electrode forming in combination a fourth MIS type field effect transistor; s) a second conductive material provided in said second groove and electrically interconnecting said third drain region and said fourth drain region to form a second complementary field effect transistor, said first and second conductive material being coupled to said third and fourth gate electrodes and to said first and second gate electrodes, respectively to form a flip-­flop circuit; t) an insulating wall region formed between said first and second drain regions and between said third and fourth drain regions; u) a first switching transistor having a first control gate coupled to a word line and capable of providing a conduction path between a first bit line and said first conductive material; and v) a second switching transistor having a second control gate coupled to said word line and capable of providing a conduction path between a second bit line and said second conductive material.

Claim 14

A complementary field effect transistor as set forth in claim 1, in which said first and second gate electrodes are formed by a single conductive hollow member.