EP0283230A2
Expired / Lapsed
EP
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A register circuit
Assignee: Fujitsu Ltd
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Filing: 1988-03-14
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Granted: —
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Expires: 2008-03-14
Abstract
Abstract A register circuit comprising a plurality of registers (R1...R7) commonly receiving a data signal (D(in)) and respective selections signals (A1...A7), each of the registers including a first input terminal (D) for receiving the data signal; a second input terminal (A) for receiving a corresponding one of the selection signals; an output terminal (Q) for outputting a stored data signal; a storing unit (M), connected to the output terminal, for storing the data signal; and a control unit (C), connected to the storing unit (M), the first input terminal (D), the second input terminal (A), and the output terminal (Q), for transferring the data signal to the storing unit when the data signal represents "1" and the selection signal is effective, and resetting the storing unit when the data signal represents "1" and the selection signal is not effective.
Inventors
- 👤 Hiroyuki Fujiyama
- 👤 Sinji Nishikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:27
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G06F9/30; G11C7/1078
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
128 words
A register circuit comprising: a plurality of registers arranged to receive a common data signal and to receive respective selection signals, each of said registers including a first input terminal for receiving the data signal, a second input terminal for receiving a corresponding one of the selection signals, an output terminal for outputting a stored data signal, storing means, connected to said output terminal, for storing the data signal, and control means, connected to said storing means, said first input terminal, said second input terminal, and said output terminal, for transferring the data signal to the storing means when the selection signal is effective and for resetting said storing means when the data signal is already stored in said storing means and the selection signal is not effective.
Claim 2
Dependent Claim
128 words
A register circuit comprising: a plurality of registers arranged to receive a common data signal and to receive respective selection signals, each of said registers including a first input terminal for receiving the data signal, a second input terminal for receiving a corresponding one of the selection signals, an output terminal for outputting a stored data signal, storing means, connected to said output terminal, for storing the data signal, and control means, connected to said storing means, said first input terminal, said second input terminal, and said output terminal, for transferring the data signal to the storing means when the selection signal is effective and for resetting said storing means when the data signal is already stored in said storing means and the selection signal is not effective.
Claim 3
Dependent Claim
63 words
A register circuit according to claim 1, wherein said control means comprises: a first NAND gate receiving the data signal and the corresponding selection signal, a second NAND gate receiving the stored data signal and an inverted signal of the data signal, and a third NAND gate receiving outputs of the first and second NAND gates and being connected to said storing means.
Claim 4
Dependent Claim
33 words
A register circuit according to claim 1 or 2, wherein said storing means comprises a flip-flop circuit connected to said control means, and means for initially setting the flip-flop to a predetermined state.
Claim 5
Dependent Claim
42 words
A register circuit according to claim 1, 2 or 3, wherein said register circuit receives a plurality of data signals, said registers are divided into a plurality of groups, and each of said groups receives a corresponding one of the data signals.
Claim 6
Dependent Claim
105 words
A register comprising: a first input terminal for receiving a data signal, a second input terminal for receiving a selection signal, an output terminal for outputting a stored data signal, storing means, connected to said output terminal, for storing the data signal, and control means, connected to said storing means, said first input terminal, said second input terminal, and said output terminal, for transferring the data signal to the storing means when the data signal has a predetermined value and the selection signal is effective, and resetting said storing means when the data signal has the predetermined value and the selection signal is not effective.
Claim 7
Dependent Claim
105 words
A register comprising: a first input terminal for receiving a data signal, a second input terminal for receiving a selection signal, an output terminal for outputting a stored data signal, storing means, connected to said output terminal, for storing the data signal, and control means, connected to said storing means, said first input terminal, said second input terminal, and said output terminal, for transferring the data signal to the storing means when the data signal has a predetermined value and the selection signal is effective, and resetting said storing means when the data signal has the predetermined value and the selection signal is not effective.
Claim 8
Dependent Claim
30 words
A register circuit comprising a plurality of registers as claimed in claim 5, wherein the registers are arranged to receive a common data signal and to receive respective selection signals.
Claim 9
Dependent Claim
60 words
A register circuit as claimed in claim 6, wherein, in use, only one of said selection signals is effective at a time, whereby when said data signal has the predetermined value, the storing means of that one of the registers receiving the effective selection signal stores the data signal, and the storing means of all the other registers are reset.
Claim 10
Dependent Claim
21 words
A register circuit as claimed in claim 5,6 or 7, wherein the predetermined value of the data signal represents a "1".
References Cited (Backward Citations)
No citation records indexed.
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