EP0282227A1
Expired / Lapsed
EP
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Signal switching processor
Assignee: British Telecommunications PLC
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Filing: 1988-03-02
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Granted: —
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Expires: 2008-03-02
Abstract
Abstract A signal switching processor has a plurality of input and output ports, and a number n of signal switching units (7,9) arranged in series between the input and output ports and coupled together so as to generate at each output port a data output signal corresponding to a data input signal supplied to a respective input port. The switching units are mounted in an array of rows, are coupled together by a perfect shuffle optical system (11), and are responsive to received data signals to modulate respective read signals incident on the switching units. Each of the leading n-1 switching units causes the modulated read signals to be reflected towards a respective reflector (25) for subsequent reflection towards the next row in the array of switching units.
Inventors
- 👤 John Edwin Midwinter
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 23:34
CPC Classifications
G; G06; G06E; G06E3/00; G06E3/006
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
122 words
A signal switching processor having a plurality of input and output ports, and a number n of signal switching units arranged in series between the input and output ports and coupled together so as to generate at each output port a data output signal corresponding to a data input signal supplied to a respective input port, the switching units being mounted in an array of rows, being coupled together by coupling means, and being responsive to received data signals to modulate respective read signals incident on the switching units, each of the leading n-1 switching units causing the modulated read signals to be reflected towards the coupling means which couples the signals with the next row in the array of switching units.
Claim 2
Dependent Claim
122 words
A signal switching processor having a plurality of input and output ports, and a number n of signal switching units arranged in series between the input and output ports and coupled together so as to generate at each output port a data output signal corresponding to a data input signal supplied to a respective input port, the switching units being mounted in an array of rows, being coupled together by coupling means, and being responsive to received data signals to modulate respective read signals incident on the switching units, each of the leading n-1 switching units causing the modulated read signals to be reflected towards the coupling means which couples the signals with the next row in the array of switching units.
Claim 3
Dependent Claim
48 words
A processor according to claim 1, the processor being adapted to perform a perfect shuffle algorithm on output port address signals supplied as data input signals to the input ports during a reset operation to select the input and output ports of the processor which are coupled together.
Claim 4
Dependent Claim
51 words
A processor according to claim 1 or claim 2, wherein each switching unit comprises a number of electro-absorption modulators one for each processor input port, the modulators being adapted to reflect an incident read beam and to modulate the read beam in accordance with data signals supplied to the switching unit.
Claim 5
Dependent Claim
23 words
A processor according to any of the preceding claims, wherein the data input and output signals and the read signals comprise optical signals.
Claim 6
Dependent Claim
69 words
A processor according to claim 4, wherein each switching unit comprises a number of photodetectors, one for each input port, a number of optical signal modulators, one for each output port, and logic means to which signals from the photodetectors are fed and which passes the signals in accordance with its logical state to respective optical signal modulators which modulate respective read beams in accordance with the signals supplied.
Claim 7
Dependent Claim
12 words
A processor according to claim 5, wherein the photodetectors comprise electro-absorbtion modulators.
Claim 8
Dependent Claim
86 words
A processor according to any of the preceding claims, wherein each switching unit comprises at least one exchange-bypass module having first and second input ports and first and second output ports, the module status being selectable such that in a first state the first input and output ports and the second input and output ports are coupled together, and in a second state the first input port is connected to the second output port and the second input port is connected to the first output port.
Claim 9
Dependent Claim
19 words
A processor according to any of the preceding claims, wherein the switching units are fabricated on a common substrate.
Claim 10
Dependent Claim
38 words
A processor according to any of the preceding claims, wherein each switching unit includes clock means for controlling operation of the switching unit, the clock means being controlled by clock signals supplied to the array of switching units.
Claim 11
Dependent Claim
21 words
A processor according to claim 9, wherein the clock signals are supplied from substantially the same position as the read signals.
Claim 12
Dependent Claim
50 words
A processor according to any of the preceding claims, further comprising an I/O member having a number of layers of microlenses through which the read signals are supplied interposed between reflective layers comprising part of the coupling means for reflecting modulated read signals towards the next succeeding signal switching unit.
Claim 13
Dependent Claim
14 words
A signal switching processor substantially as hereinbefore described with reference to the accompanying drawings.
Claim 14
Dependent Claim
14 words
A signal switching processor substantially as hereinbefore described with reference to the accompanying drawings.
References Cited (Backward Citations)
WO1987000314A1
Cited
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