EP0281215A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programmable integrated circuit logic array device having improved microprocessor connectability
Assignee: Altera Corp
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Filing: 1988-01-06
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Granted: —
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Expires: 2008-01-06
Abstract
Abstract A programmable integrated circuit logic array device having one or more of the following features: (1) a bus port for receiving data directly from or making data available directly to an associated microprocessor or other similar device, (2) an internal bus (preferably with internal bus arbitration logic for resolving competing demands for utilization of the bus) for conveying data between the bus port and the logic arrays and/or between the logic arrays themselves, (3) the ability to operate either in an edge-trigger mode (in which controlled functions such as input registers are triggered by the transitional edges of control signals) or in a flow-through mode (in which controlled functions such as input registers are triggered by the states rather than the transitional edges of the control signals), and (4) the ability to operate either in a fast mode (in which timing control signals are applied substantially directly to the elements to be controlled) or in a slow mode (in which timing control signals propagate through the logic arrays rather than being applied directly to the elements to be controlled).
Inventors
- 👤 Yiu-Fai Chan
- 👤 Chuan-Yung Hung
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 01:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
122 words
A programmable integrated circuit logic array device comprising: a plurality of macrocells each including input means for selectively receiving data applied to the macrocell and output means for selectively outputting data from the macrocell, said macrocells being divided into first and second groups, each of said groups including a plurality of macrocells; a bus including a plurality of signal conductors each of which is connected to the input means and the output means in a respective one of the macrocells in each of said groups; and control means for allowing the output means of either of said groups to output data to said bus and for preventing the output means of both of said groups from simultaneously outputting data to said bus.
Claim 2
Dependent Claim
122 words
A programmable integrated circuit logic array device comprising: a plurality of macrocells each including input means for selectively receiving data applied to the macrocell and output means for selectively outputting data from the macrocell, said macrocells being divided into first and second groups, each of said groups including a plurality of macrocells; a bus including a plurality of signal conductors each of which is connected to the input means and the output means in a respective one of the macrocells in each of said groups; and control means for allowing the output means of either of said groups to output data to said bus and for preventing the output means of both of said groups from simultaneously outputting data to said bus.
Claim 3
Dependent Claim
97 words
The device of claim 1 wherein said control means comprises: first and second transfer output ot bus means respectively associated with said first and second groups for respectively producing first and second transfer output to bus request signals when data is to be output by the associated group; and bus arbitration logic means responsive to said first and second transfer output to bus request signals for enabling the output means of the group associated with the first of said first and second transfer output to bus request signals to be applied to said bus arbitration logic means.
Claim 4
Dependent Claim
58 words
The device of claim 2 wherein said bus arbitration logic means further comprises: means responsive to said first and second transfer output to bus request signals for disabling the output means of the group not associated with the first of said first and second transfer output to bus request signals to be applied to said bus arbitration means.
Claim 5
Dependent Claim
94 words
The device of claim 3 wherein said bus arbitration logic means further comprises: means responsive to said first and second transfer output to bus request signals for disabling the output means of the group associated with the first of said first and second transfer output to bus request signals to be applied to said bus arbitration logic means when said first signal ends and for enabling the output means of the other group if the other of said transfer output to bus request signals is then still being applied to said bus arbitration means.
Claim 6
Dependent Claim
86 words
The device of claim 1 further comprising: a bus port connected to said bus and including input gate means for selectively applying to said bus data applied to said bus port by an external device and output gate means for selectively applying to said bus port for application to said external device data from said bus; and additional control means for inhibiting said input gate means while said control means is allowing the output means of either of said groups to output data to said bus.
Claim 7
Dependent Claim
32 words
The device of claim 5 further comprising: further control means for enabling said input gate means while said control means is allowing neither of said groups to output data to said bus.
Claim 8
Dependent Claim
41 words
The device of claim 6 further comprising: still further control means for allowing said output gate means to be enabled only while said control means is allowing the output means of either of said groups to output data to said bus.
Claim 9
Dependent Claim
50 words
The device of claim 1 further comprising: means for causing the input means of said group that is not outputting data to said bus to receive data from said bus so that data can be transferred from either of said groups to the other of said groups via said bus.
Claim 10
Dependent Claim
78 words
The device of claim 1 further comprising: first and second input enable means respectively associated with said first and second groups for respectively producing first and second input enable signals when data is to be input from said bus to the associated group; and means for respectively applying said first and second input enable signals to said input means of said first and second groups for enabling said input means when the associated input enable signal is produced.
Claim 11
Dependent Claim
185 words
A programmable integrated circuit logic array device for use with an external device comprising: a bus port for receiving data from said external device; input latch means connected to said bus port for selectively latching in data applied to said bus port; and control means for producing an input latch enable signal for enabling said input latch means, said control means including (1) a programmable element for producing an output signal indicative of whether a fast write mode or a slow write mode has been preselected, (2) write strobe signal processing means responsive to a write strobe signal which may be applied to said device by said external device, (3) means for generating an enable input latch enable signal, and (4) means responsive to said items 1-3 for producing said input latch enable signal in response to the occurrence of said enable input latch enable signal when said slow write mode is selected, and for producing said input latch enable signal in response to simultaneous occurrence of said enable input latch enable signal and said write strobe signal when said fast write mode is selected.
Claim 12
Dependent Claim
185 words
A programmable integrated circuit logic array device for use with an external device comprising: a bus port for receiving data from said external device; input latch means connected to said bus port for selectively latching in data applied to said bus port; and control means for producing an input latch enable signal for enabling said input latch means, said control means including (1) a programmable element for producing an output signal indicative of whether a fast write mode or a slow write mode has been preselected, (2) write strobe signal processing means responsive to a write strobe signal which may be applied to said device by said external device, (3) means for generating an enable input latch enable signal, and (4) means responsive to said items 1-3 for producing said input latch enable signal in response to the occurrence of said enable input latch enable signal when said slow write mode is selected, and for producing said input latch enable signal in response to simultaneous occurrence of said enable input latch enable signal and said write strobe signal when said fast write mode is selected.
Claim 13
Dependent Claim
55 words
The device of claim 10 further comprising: logic array means having a plurality of inputs; and means for applying to one of said inputs the signal applied to said write strobe signal processing means so that the signal applied to said write strobe signal processing means can also be used by said logic array means.
Claim 14
Dependent Claim
180 words
A programmable integrated circuit logic array device for use with an external device comprising: a bus port for selectively transmitting data to said external device; and control means for producing a bus port output enable signal for enabling said bus port to transmit data to said external device, said control means including (1) a programmable element for producing an output signal indicative of whether a fast read mode or a slow read mode has been preselected, (2) read strobe signal processing means responsive to a read strobe signal which may be applied to said device by said external device, (3) means for generating an enable bus port output enable signal, and (4) means responsive to said items 1-3 for producing said bus port output enable signal in response to the occurrence of said enable bus port output enable signal when said slow read mode is selected, and for producing said bus port output enable signal in response to simultaneous occurrence of said enable bus port output enable signal and said read strobe signal when said fast read mode is selected.
Claim 15
Dependent Claim
180 words
A programmable integrated circuit logic array device for use with an external device comprising: a bus port for selectively transmitting data to said external device; and control means for producing a bus port output enable signal for enabling said bus port to transmit data to said external device, said control means including (1) a programmable element for producing an output signal indicative of whether a fast read mode or a slow read mode has been preselected, (2) read strobe signal processing means responsive to a read strobe signal which may be applied to said device by said external device, (3) means for generating an enable bus port output enable signal, and (4) means responsive to said items 1-3 for producing said bus port output enable signal in response to the occurrence of said enable bus port output enable signal when said slow read mode is selected, and for producing said bus port output enable signal in response to simultaneous occurrence of said enable bus port output enable signal and said read strobe signal when said fast read mode is selected.
Claim 16
Dependent Claim
55 words
The device of claim 12 further comprising: logic array means having a plurality of inputs; and means for applying to one of said inputs the signal applied to said read strobe signal processing means so that the signal applied to said read strobe signal processing means can also be used by said logic array means.
Claim 17
Dependent Claim
203 words
A programmable integrated circuit logic array device comprising: a bus for conveying data applied to said bus; output latch means connected to said bus for selectively storing data applied to said latch means; output gate means for selectively applying data stored by said latch means to said bus; and control means for producing an output latch enable signal for enabling said latch means to store said data applied to said latch means, said control means including (1) a programmable element for producing an output signal indicative of whether a fast output latch enable mode or a slow output latch enable mode has been preselected, (2) clock signal processing means responsive to a clock signal which may be applied to said clock signal processsing means, (3) means for generating an enable output latch enable signal, and (4) means responsive to said items 1-3 for producing said output latch enable signal in response to the occurrence of said enable output latch enable signal when said slow output latch enable mode is selected, and for producing said output latch enable signal in response to simultaneous occurrence of said enable output latch enable signal and said clock signal when said fast output latch enable mode is selected.
Claim 18
Dependent Claim
203 words
A programmable integrated circuit logic array device comprising: a bus for conveying data applied to said bus; output latch means connected to said bus for selectively storing data applied to said latch means; output gate means for selectively applying data stored by said latch means to said bus; and control means for producing an output latch enable signal for enabling said latch means to store said data applied to said latch means, said control means including (1) a programmable element for producing an output signal indicative of whether a fast output latch enable mode or a slow output latch enable mode has been preselected, (2) clock signal processing means responsive to a clock signal which may be applied to said clock signal processsing means, (3) means for generating an enable output latch enable signal, and (4) means responsive to said items 1-3 for producing said output latch enable signal in response to the occurrence of said enable output latch enable signal when said slow output latch enable mode is selected, and for producing said output latch enable signal in response to simultaneous occurrence of said enable output latch enable signal and said clock signal when said fast output latch enable mode is selected.
Claim 19
Dependent Claim
53 words
The device of claim 14 further comprising: logic array means having a plurality of inputs; and means for applying to one of said inputs the signal applied to said clock signal processing means so that the signal applied to said clock signal processing means can also be used by said logic array means.
Claim 20
Dependent Claim
165 words
The device of claim 14 further comprising: additional control means for producing an output gate enabling signal for enabling said output gate means to apply the data stored by said latch means to said bus, said additional control means including (a) a programmable element for producing an output signal indicative of whether or not a fast read mode or a slow read mode has been preselected, (b) read strobe signal processing means responsive to a read strobe signal which may be applied to said read strobe signal processing means, (c) means for generating an enable output gate enabling signal, and (d) means responsive to said items a-c for producing said output gate enabling signal in response to the occurrence of said enable output gate enabling signal when said slow read mode is selected, and for producing said output gate enabling signal in response to simultaneous occurrence of said enable output gate enabling signal and said read strobe signal when said fast read mode is selected.
Claim 21
Dependent Claim
98 words
A programmable integrated circuit logic array device comprising: programmable means for producing an output signal indicative of whether a flow-through mode or an edge-trigger mode has been preselected; means for generating a latch enabling control signal; and input latch means for storing data applied to said latch means in response to a predetermined logical state of said latch enabling control signal when said flow-through mode is selected, and for storing data applied to said latch means in response to a predetermined change in the logical state of said latch enabling control signal when said edge-trigger mode is selected.
Claim 22
Dependent Claim
98 words
A programmable integrated circuit logic array device comprising: programmable means for producing an output signal indicative of whether a flow-through mode or an edge-trigger mode has been preselected; means for generating a latch enabling control signal; and input latch means for storing data applied to said latch means in response to a predetermined logical state of said latch enabling control signal when said flow-through mode is selected, and for storing data applied to said latch means in response to a predetermined change in the logical state of said latch enabling control signal when said edge-trigger mode is selected.
Claim 23
Dependent Claim
153 words
A programmable integrated circuit logic array device comprising: logic array means for producing a logic array output signal; an input/output pin; gate means for selectively applying said logic array output signal to said input/output pin; programmable means for producing an output signal indicative of whether a logic array feedback mode or an I/O feedback mode has been preselected; and multiplexer means having first and second input terminals selectively connectable to an output terminal, said logic array output signal being applied to said first input terminal, said second input terminal being connected to said input/output pin, and said output terminal being connected to an input of said logic array means, said multiplexer means responding to said programmable means by connecting said first input terminal and said output terminal when said logic array feedback mode is selected, and by connecting said second input terminal and said output terminal when said I/O feedback mode is selected.
Claim 24
Dependent Claim
153 words
A programmable integrated circuit logic array device comprising: logic array means for producing a logic array output signal; an input/output pin; gate means for selectively applying said logic array output signal to said input/output pin; programmable means for producing an output signal indicative of whether a logic array feedback mode or an I/O feedback mode has been preselected; and multiplexer means having first and second input terminals selectively connectable to an output terminal, said logic array output signal being applied to said first input terminal, said second input terminal being connected to said input/output pin, and said output terminal being connected to an input of said logic array means, said multiplexer means responding to said programmable means by connecting said first input terminal and said output terminal when said logic array feedback mode is selected, and by connecting said second input terminal and said output terminal when said I/O feedback mode is selected.
Claim 25
Dependent Claim
128 words
The device of claim 18 further comprising: a bus for conveying data applied to said bus; additional programmable means for producing an output signal indicative of whether or not a bus mode has been selected; additional multiplexer means having first and second input ports selectively connectable to an output port, said input/output pin being connected to said first input port, said bus being connected to said second input port, and said output port being connected to an additional input of said logic array means, said additional multiplexer means responding to said additional programmable means by connecting said first input port to said output port when said bus mode is not selected, and by connecting said second input port to said output port when said bus mode is selected.
Claim 26
Dependent Claim
34 words
The device of claim 19 wherein said additional logic array input comprises: input latch means for selectively storing said additional multiplexer output port signal and applying the stored signal to said logic array means.
Claim 27
Dependent Claim
131 words
The device of claim 19 further comprising: additional programmable means for producing an output signal indicative of whether a flow-through mode or an edge-trigger mode has been preselected; control means for generating a latch enabling control signal; and input latch means connected between said additional multiplexer output port and said additional logic array input for storing said additional multiplexer output signal and applying the stored signal to said additional logic array input in response to a predetermined logical state of said latch enabling control signal when said flow-through mode is selected, and for storing said additional multiplexer output signal and applying the stored signal to said additional logic array input in response to a predetermined change in the state of said latch enabling control signal when said edge-trigger mode is selected.
Claim 28
Dependent Claim
124 words
A programmable integrated circuit logic array device comprising: logic array means for producing a logic array output signal, said logic array means having first and second inputs; means for applying said logic array output signal to said first input; an input/output pin; means for applying the signal applied to said input/output pin to said second input; programmable means for producing an output signal indicative of whether a dual feedback mode or an output mode has been preselected; and gate means responsive to said programmable means for applying said logic array output signal to said input/output pin when said output mode is selected, and for interrupting the connection between said logic array output signal and said input/output pin when said dual feedback mode is selected.
Claim 29
Dependent Claim
124 words
A programmable integrated circuit logic array device comprising: logic array means for producing a logic array output signal, said logic array means having first and second inputs; means for applying said logic array output signal to said first input; an input/output pin; means for applying the signal applied to said input/output pin to said second input; programmable means for producing an output signal indicative of whether a dual feedback mode or an output mode has been preselected; and gate means responsive to said programmable means for applying said logic array output signal to said input/output pin when said output mode is selected, and for interrupting the connection between said logic array output signal and said input/output pin when said dual feedback mode is selected.
Claim 30
Dependent Claim
144 words
A programmable integrated circuit logic array device for use with external apparatus comprising: a bus port for selectively outputting from said device data read by said external apparatus, and for inputting to said device data written by said external apparatus; programmable means for producing an output signal indicative of whether a write precedence mode or a read precedence mode has been preselected; and control means responsive to read and write request signals produced by said external apparatus for enabling said bus port to output data from said device in response to a read request signal unless said write precedence mode is selected and a write request signal is also present, and for enabling said bus port to input data to said device in response to a write request signal unless said read precedence mode is selected and a read request signal is also present.
Claim 31
Dependent Claim
144 words
A programmable integrated circuit logic array device for use with external apparatus comprising: a bus port for selectively outputting from said device data read by said external apparatus, and for inputting to said device data written by said external apparatus; programmable means for producing an output signal indicative of whether a write precedence mode or a read precedence mode has been preselected; and control means responsive to read and write request signals produced by said external apparatus for enabling said bus port to output data from said device in response to a read request signal unless said write precedence mode is selected and a write request signal is also present, and for enabling said bus port to input data to said device in response to a write request signal unless said read precedence mode is selected and a read request signal is also present.
References Cited (Backward Citations)
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