A/D Converter

Claim 2

An A/D converter for converting an analog input signal (Vin) into a digital output signal (Dout) having an n-bit binary code, and comprising: first A/D conversion means (13) for A/D-converting the analog input signal (Vin) into a first digital output (D13) corresponding to upper a-bit data of the n-bit digital output signal (Dout); first sample-hold means (15a) for sampling a signal level of the analog input signal (Vin) and outputting a first hold signal (V15a); second sample-hold means (15b) for sampling a signal level of the analog input signal (Vin) and outputting a second hold signal (V15b); first switching means (S1, S2) for, in synchronism with the A/D conversion operation of said first A/D conversion means (13), selecting the second hold signal (V15b) from said second sample-hold means (15b) during a period in which said first sample-hold means (15a) samples the signal level of the analog input signal (Vin), and selecting the first hold signal (V15a) from said first sample-hold means (15a) during a period in which said second sample-hold means (15b) samples the signal level of the analog input signal (Vin); and second A/D conversion means (14, 140) for A/D-­converting one of the first and second hold signals (V15a, V15b) selected by said first switching means (S1, S2), and outputting a second digital output (D14) corre­sponding to lower b-bit data of the n-bit digital output signal (Dout), said first and second digital outputs (D13, D14) being combined to provide said n-bit digital output signal (Dout).

Claim 3

An A/D converter according to claim 1, further comprising: third sample-hold means (17a) for sampling a signal level of the analog input signal (Vin) and outputting a third hold signal (V17a); fourth sample-hold means (17b) for sampling a signal level of the analog input signal (Vin) and outputting a fourth hold signal (V17b); fifth sample-hold means (17c) for sampling a signal level of the analog input signal (Vin) and outputting a fifth hold signal (V17c); second switching means (S3, S4) for, in synchronism with the A/D conversion operation of said first A/D conversion means (13), selecting the fifth hold signal (V17c) from said fifth sample-hold means during a period in which one of said third and fourth sample-hold means (17a, 17b) samples the signal level of the analog input signal (Vin), selecting the fourth hold signal (V17b) from said fourth sample-hold means (17b) during a period in which one of said fifth and third sample-hold means (17c, 17a) samples and signal level of the analog input signal (Vin), and selecting the third hold signal (V17a) from said third sample-hold means (17a) during a period in which one of said fourth and fifth sample-hold means (17b, 17c) samples the signal level of the analog input signal (Vin); and third A/D conversion means (19, 190) for A/D-­converting one of the third through fifth hold signals (V15a - V15c) selected by said second switching means (S3, S4), and outputting a third digital output (D19) corresponding to further lower c-bit data of the n-bit digital output signal (Dout), said first through third digital outputs (D13, D14, D19) being combined to provide said n-bit digital output signal (Dout).

Claim 4

An A/D converter according to claim 1, characterized in that said second A/D conversion means (140) includes: voltage comparison means (21), coupled to said first A/D conversion means (13), for alternately comparing a first reference voltage (Vref) with one of said first and second hold signals (V15a, V15b), said first reference voltage (Vref)being changed in accor­dance with a content of the first digital output (D13).

Claim 5

An A/D converter according to claim 1, chara­cterized in that said first A/D conversion means (13) includes: first reference voltage generator means (11a) for generating a plurality of first reference voltages (Vr); a first chopper comparator (SO1, SO2, SO3, CO, IO), couopled to said first reference voltage generator means (11a), and being alternatively responsive to said analog input signal (Vin) and one (Vr(1)) of said first reference voltages, for provideing a first comparison output as a result of comparison between said analog input signal (Vin) and one (Vr (1)) of said first reference voltages; and first encoder means (12a), coupled to said first chopper comparator (SO1, SO2, SO3, CO,IO) to provide said first digital ouptut (D13), and characterized in that said second A/D conver­sion means (140) includes: second reference voltage generator means (11b), coupled to said first A/D conversion means (13), for generating a plurality of second reference voltages (Vref) the value of each of which depends on contents of said first digital outpu (D13); a second chopper comparator (S11, S12, S13, C1, I1), coupled to said second reference voltage generator means (11b), and being alternatively responsive to said analog input signal (Vin) and one (Vref(1)) of said second reference voltages, for providing a second comparison output as a result of comparison between said analog input signal (Vin) and one (Vref(1)) of said second reference voltages; a third chopper comparator (S21, S22, S23, C2, I2), coupled to said second reference voltage generator means (11b), and being alternatively responsive to said analog input signal (Vin) and another one (Vref(1)) of said second reference voltages, for providing a third comparison output as as result of comparison between said analog inpout signal (Vin) and another one (Vref(1)) of said second reference voltages, said third chopper comparator (S21, S22, S23, C2, I2) being coupled in parallel to said second chopper comparator (S11, S12, S13, C1, I1), and second encoder means (12b), coupled to said second and third chopper comparators (S22, S12, S13, C1, I1; S21, S22, S23, C2, I2), for encoding said seacond and third comparison outputs (V21), to provide said second digital output (D14).

Claim 6

An A/D converter according to claim 2, chara­cterized in that said second A/D conversin means (140) includes: first voltage comparison means (21), coupled to said first A/D conversion means (13), for alternately comparing a first reference voltage (Vref), which changes in accordance with a content of the first digital output (D13), with one of said first and second hold signals (V15a, V15b), and characterized in that said third A/D conversion means (190) includes: second voltage comparison means (22), coupled to said first and second A/D conversion means (13, 14), for sequentially comparing a second reference voltage (Vs), which changes in accordance with contents of the first and second digital outputs (D13, D14), with one of the first through third hold signals (V15a - V15c).

Claim 7

An A/D converter according to claim 2, chara­cterized in that said first A/D conversion means (13) includes: first reference voltage generator means (11a) for generating a plurality of first reference voltages (Vr); a first chopper comparator (SO1, SO2, SO3, CO, IO), coupled to said first referencd voltage generator means (11a), and being alternatively responsive to said analog input signal (Vin) and one (Vr(1)) of said first refer­ence voltages, for providing a first comparison output as a result of comparison between said analog input signal (Vin) and one (Vr(1)) of said first reference voltages; and first encoder means (12a), coupled to said first chopper comparator (SO1, SO2, SO3, CO, IO), for encoding said first comparison output (V20) to provide said first digital output (D13), characterized in that said second A/D conversion means (140) includes: second reference voltage generator means (11b), coupled to said first A/D conversion means (13), for generating a plurality of second reference voltages (Vref) the value of each of which depends on contents of said first digital output (D13); a second chopper comparator (S11, S12, S13, C1, I1), coupled to said second reference voltage generator means (11b), and being alternatively responsive to said analog input signal (Vin) and one (Vref(1)) of said second reference voltages, for providing a second comparison output as a result of comparison between said analog input signal (Vin) and one (Vref(1)) of said second reference voltages; a third chopper comparator (S21, S22, S23, C2, I2), coupled to said second reference voltage generator means (11b), and being alternatively responsive to said analog input signal (Vin) and one (Vref(1)) of said second reference voltages, for providing a third comparison output as a result of comparison between said analog input signal (Vin) and one (Vref(1)) of said second reference voltages, said third chopper comparator (S21, S22, S23, C2, I2) being coupled in parallel to said second chopper comparator (S11, S12, S13, C1, I1); and second encoder means (12b), coupled to said second and third chopper comparators (S11, S12, S13, C1, I1; S21, S22, S23, C2, I2), for encoding said second and third comparison outpus (V21), to provide said second digital output (D14), and characterized in that said third A/D conversion means (190) includes: third reference voltage generator means (11c), coupled to said second A/D conversion means (140), for generating a plurality of third reference voltages (Vs) the value of each of which depends on contents of said first and second digital outputs (D13, D14); a fourth chopper comparator (S31, S32, S33, C10, I10), coupled to said third reference voltage generator means (11c), and being alternatively responsive to said analog input signal (Vin) and one (Vs(1)) of said third reference voltages, for providing a fourth comparison output as a result of comparison between said analog input signal (Vin) and one (Vs(1)) of said third reference voltages; a fifth chopper comparator (S41, S42, S43, C20, I20), coupled to said third reference voltage generator means (11c), and being alternatively responsive to said analog input signal (Vin) and one (Vs (1)) of said third reference voltages, for providing a fifth comparison output as a result of comparison between said analog input signal (Vin) and one (Vs(1)) of said third reference voltages; a sixth chopper comparator (S51, S52, S53, C30, I30), coupled to said third reference voltage generator means (11c), and being alternatively responsive to said analog input signal (Vin) and one (Vs(1)) of said third reference voltages, for providing a sixth comparison output as as result of comparison between said analog input signal (Vin) and one (Vs (1)) of said third reference voltages, said fourth, fifth, and sixth chopper comparators being coupled in parallel to one another; and third encoder means (12c), coupled to said fourth, fifth, and sixth chopper comparators, for encoding said fourth, fifth, and sixth comparison outputs (V22), to provide said third digital output (D19).

Claim 8

An A/D converter according to claim 4, characterized in that at least one of said first, second, and third chopper comparators includes: first switch means (SW1) for selectively supplying a comparison reference signal (Vin1) to one terminal (N1) of a first capacitor (CO1); second switch means (SW2) for selectively supplying a signal (Vin2) to be compared to said one terminal (N1) of said first capacitor (CO1); a buffer amplifier (BO), an input terminal of which is connected to the other terminal (N2) of said first capacitor (CO1), and which has a high input impedance and a low output impedance; a second capacitor (CO2), one terminal (N3) of which is connected to an output terminal of said buffer amplifier (BO); an inverting amplifier (IO), an input terminal of which is connected to the other terminal (N4) of said second capacitor (CO2); third switch means (SW3) for selectively connecting the input and output terminals of said inverting ampli­fier (IO); and fourth switch means (SW4) for selectively supplying a predetermined voltage (Vr) to said other terminal (N2) of said first capacitor (CO1).

Claim 9

An A/D converter according to claim 6, characterized in that at least one of said first through sixth chopper comparators includes: first switch means (SW1) for selectively supplying a comparison reference signal (Vin1) to one terminal (N1) of a first capacitor (CO1); second switch means (SW2) for selectively supplying a signal (Vin2) to be compared to said one terminal (N1) of said first capacitor (CO1); a buffer amplifier (BO), an input terminal of which is connected to the other terminal (N2) of said first capacitor (CO1), and which has a high input impedance and a low output impedance; a second capacitor (CO2), one terminal (N3) of which is connected to an output terminal of said buffer amplifier (BO); an inverting amplifier (IO), an input terminal of which is connected to the other terminal (N4) of said second capacitor (CO2); third switch means (SW3) for selectively connecting the input and output terminals of said inverting ampli­fier (IO); and fourth switch means (SW4) for selectively supplying a predetermined voltage (Vr) to said other terminal (N2) of said first capacitor (CO1).

Claim 10

An A/D converter according to claim 4, characterized in that at least one of said first, second, and third chopper comparators includes: first switch means (SW1) for selectively supplying a comparison reference signal (Vin1) to one terminal (N1) of a first capacitor (CO1); second switch means (SW2) for selectively supplying a signal (Vin2) to be compared to said one terminal (N1) of said first capacitor (CO1); a second capacitor (CO2), one terminal of which is connected to the other terminal (N2) of said first capacitor (CO1); an inverting amplifier, an input terminal of which is connected to the other terminal (N4) of said second capacitor (CO2); third switch means (SW3) for selectively connecting the input and output terminals of said inverting ampli­fier (IO); and fourth switch means (SW4) for selectively supplying a predetermined voltage (Vr) to said other terminal (N2) of said first capacitor (CO1).

Claim 11

An A/D converter according to claim 6, characterized in that at least one of first through sixth chopper comparators includes: first switch means (SW1) for selectively supplying a comparison reference signal (Vin1) to one terminal (N1) of a first capacitor (CO1); second switch means (SW2) for selectively supplying a signal (Vin2) to be compared to said one terminal (N1) of said first capacitor (CO1); a second capacitor (CO2), one terminal of which is connected to the other terminal (N2) of said first capacitor (CO1); an inverting amplifier, an input terminal of which is connected to the other terminal (N4) of said second capacitor (CO2); third switch means (SW3) for selectively connecting the input and output terminals of said inverting ampli­fier (IO); and fourth switch means (SW4) for selectively supplying a predetermined voltage (Vr) to said other terminal (N2) of said first capacitor (CO1).