Digital interface device for PCM data, in particular for digital telephone, data processing or image processing system

Claim 2

A digital interface device for PCM data, in particular for digital telephone, data processing or image processing systems, characterized in that it comprises a reception memory (162), connected to a PCM channel (17) and receiving therefrom groups of data to be stored, a control processor (120) connected to said reception memory (162) and receiving therefrom data records formed by a plurality of said data groups, a transmission memory (163), connected to said control processor (120) and receiving data records therefrom, to be transmitted onto said PCM channel (17) or a different PCM channel, said reception and transmission memories (162,163) being divided into a plurality of buffers for storing said data records selectively received and to be transmitted at present time intervals, and in that it furthermore comprises a timing phase sequencer (164) and a protocol controller (165), both connected to said reception and transmission memories (162,163) and to said control processor (120) for detecting beginning of reception of a data record, for controlling correct storage of said data groups of a same record in said reception memory, for sending complete received data records towards said control processor and for allowing transmission of a data record from said transmission memory in said data groups onto said PCM channel (17) at preset time intervals.

Claim 3

An interface device according to claim 1, characterized in that each said data record comprises a first data group having a preset configuration indicative of record start, a second data group indicative of the length of said record and at least one further data group, said data group being received and/or transmitted at different time intervals, spaced apart from each other of a preset time, characterized in that said protocol controller (165) comprises a reception stage including a record start detector (183), connected to said PCM channel (17) for detecting said first data group and generating a record start signal, a reception state sequencer (177), connected to said record start detector (183) for enabling said record start detector (183) at the end of a data record reception, a reception current address memory (173), connected to said PCM channel (17) and addressing said reception memory (120) for grouping the data groups of a same record recieved at said different time intervals, a down-counter (179) enabled by said reception state sequencer and connected to said reception current address memory (173) for receiving memory addresses and generating updated memory addresses for storage of successive data groups, a comparator (181), connected to said state sequencer (177) for comparing the updated memory addresses generated by said down-counter (179) to a zero value and generating a reception end signal, as well as a buffer memory (185), connected to said comparator (181) for storing the address of a memory location of said reception memory (162) storing an entire record and for sending a complete record signal to said control processor (120).

Claim 4

An interface device according to the preceding claims, characterized in that said reception stage of said protocol controller (165) comprises a multiplexer (167) having a first input connected to said PCM channel (17), a second input connected to said down-counter (179), a selection input, connected to said reception state sequencer (177) and an output connected to said reception current address memory (173).

Claim 5

An interface device according to claim 2, characterized in that said reception stage of said protocol controller (165) further comprises a reception state memory (175) connected to and controlled by said reception state sequencer (177) for storing a state configuration selectively corresponding to a record start waiting state, a second data group waiting state and a data reception state.

Claim 6

An interface device according to one or more of the preceding claims, characterized in that said protocol controller (165) furthermore comprises a transmission stage including a transmission state sequencer (178), a transmission start detector (184), connected to said transmission memory (163) for detecting said second data group and generating a record start signal sent to said transmission state sequencer (178), a transmission current address memory (174), addressing said transmission memory (163) for allowing transmission in sequence of said data records at said different time intervals, a down-counter (180), enabled by said transmission state sequencer (178) and connected to said transmission current address memory for receiving memory addresses and generating updated memory addresses fed to said transmission current address memory (163), a comparator (182), enabled by said transmission state sequencer (178) and connected to said down-counter (180) for comparing with zero said updated memory addresses and generating a transmission end signal when said updated memory addresses are equal to zero.

Claim 7

An interface device according to one or more of the preceding claims, characterized in that said transmission stage furthermore comprises a multiplexer (168) having a first input connected to the output of said transmission memory (163), a second input connected to said transmission down-counter (180), a selection input connected to said transmission state sequencer (178) and an output connected to said transmission current address memory (174).

Claim 8

An interface device according to claim 5, characterized in that said transmission stage of said protocol controller (165) further comprises a transmission state memory (176) connected to and controlled by said transmission state sequencer (178) for storing a state configuration selectively corresponding to a record start waiting state, a second data group transmission state and a data transmission state.

Claim 9

An interface device according to one or more of the preceding claims, characterized in that it comprises a serial/parallel converter (160) having an input connected to said PCM channel (17) and an output connected to said reception memory (162) and said protocol controller (165), and a parallel/serial converter (161) having a first data input connected to said transmission memory (163), a second control input connected to said protocol controller (165) and an output connected to said PCM channel (17).

Claim 10

A process for digital data exchange between a processing unit and a PCM line, comprising a time sharing transmission of data groups forming a data record at set time intervals of successive time periods, characterized in that said time sharing transmission comprises transmission of a first data group indicative of transmission start in said preset time interval of a first time period, transmission of a second data group indicative of the number of the data groups forming said data record in said preset time interval of a second time period, successive to said first time period, and successive transmission of further data groups in said time intervals of successive time periods.

Claim 11

A process for digital data exchange between a processing unit and a PCM line, comprising a time sharing transmission of data groups forming a data record at set time intervals of successive time periods, characterized in that said time sharing transmission comprises transmission of a first data group indicative of transmission start in said preset time interval of a first time period, transmission of a second data group indicative of the number of the data groups forming said data record in said preset time interval of a second time period, successive to said first time period, and successive transmission of further data groups in said time intervals of successive time periods.

Claim 12

A process according to the preceding claim, characterized in that each of said time periods comprises 256 time intervals and each of said data groups comprises 8 bits.