Header driven packet switching system and method

Claim 2

A header driven packet switching system including hardware (6a) for routing a data packet coming through one of incoming lines (11 - 1n) and rewriting a header of said data packet according to routing information such as a virtual call number and a line number added to said header of said data packet, comprising:

Claim 3

a plurality of packet header processing circuits (41, 42, ...) disposed independently from said incoming lines, for controlling the routing and header rewriting of said data packet; and connecting means (3) for detecting a free circuit from among said plurality of packet header processing circuits, and for connecting said one incoming line with said free packet header processing circuit.

Claim 4

a plurality of packet header processing circuits (41, 42, ...) disposed independently from said incoming lines, for controlling the routing and header rewriting of said data packet; and connecting means (3) for detecting a free circuit from among said plurality of packet header processing circuits, and for connecting said one incoming line with said free packet header processing circuit.

Claim 5

A header driven packet switching system as set forth in claim 1, further comprising; a plurality of incoming circuits (21, 22, ...) connected between said incoming lines and said packet header processing circuits, each of said incoming circuit comprising; a first buffer (215) for temporarily storing a data packet coming through an incoming line; a scanning circuit (211) for scanning said plurality of packet header processing circuits; first drive means (212) for driving said free header processing circuits; an incoming line number storing means (213); and first control means (214) for controlling said first buffer, said scanning circuit, said first drive means, and said incoming line number storing means; whereby, when said first buffer receives a data packet, said first control means starts a scan by said scanning circuit to determine a free packet header processing circuit from among said plurality of packet header circuits, modifies said received data packet stored in said first buffer by adding said incoming line number to said received data packet and stores the modified data packet into said first buffer, and drives said first drive means to open said free packet header processing circuit for receiving said modified data packet.

Claim 6

A header driven packet switching system as set forth in claim 2, wherein said incoming circuits are respectively connected to said incoming lines, and the ratio of the number of said incoming circuits and the number of said packet header processing circuits is arbitrarily determined.

Claim 7

A header driven packet switching system as set forth in claim 2, wherein each of said packet header processing circuits comprises: second drive means (411) connected to said scanning circuit (211) in each of said incoming line circuits, for determining whether or not said packet header processing circuit is free; a priority control circuit (412) connected to said first drive means (212) in each of said incoming circuits, for controlling competition among process requests from a plurality of said incoming line circuits to determine which incoming line circuit is to be processed; first gate means (417) connected to said first buffer (215) in each of said incoming circuits, for introducing said modified data packet stored in said first buffer to said free packet header processing circuit; second control means (416) for controlling said second drive means and said first gate means, whereby when said priority control circuit determines which incoming line circuit is to be processed, said second control means starts to operate to open said first gate means.

Claim 8

A header driven packet switching system as set forth in claim 2, wherein said connecting means (3) comprises said scanning circuit (211), said first drive means (212), said control means (214), said second drive means (411), said priority control means (412), said first gate means (417), and said second control means (416).

Claim 9

A header driven packet switching system as set forth in claim 4 or 5, further comprising a plurality of outgoing line circuits (5a, 5b) and wherein each of said packet header processing circuits further comprises: a second buffer (418) for temporarily storing said modified data packet passed through said first gate means (417); routing conversion table means (413) for storing a correspondence between an incoming routing information and an outgoing routing information; third drive means (414) for generating an outgoing connection request; and a receiving circuit (415) for receiving a connection complete signal; whereby, when said second buffer receives said modified data packet from said first buffer through said first gate means, said second control means starts to operate to close said first gate means and to look up said routing conversion table means (413) to determine said outgoing routing information including the next virtual call number and the outgoing line number, and to rewrite the header of said modified data packet in said second buffer with said outgoing routing information, and said second control means drives said third drive means (414) to output said outgoing connection request to a selected one of said outgoing line circuits corresponding to said outgoing line number.

Claim 10

A header driven packet switching system as set forth in claim 6, wherein each of said outgoing line circuits comprises: stack memory means (515) for sequentially storing said outgoing connection requests from said third drive means in a sequence of the generation of said outgoing connection requests; fourth drive means (512) for generating said connection complete signal; second gate means (514) having a plurality of gates each for gating said data packet stored in said second buffer to a selected outgoing line (51 or 52); and third control means (513) for controlling said stack memory means, said fourth drive means, and said second gate means whereby, when said third control means detects an outgoing connection request in said stack memory means, said third control means drives said second gate means (514) to open a gate corresponding to the selected outgoing line and drives said fourth drive means (512) to transfer said connection complete signal from said fourth drive means through said receiving circuit (415) to said second control means (416) so that second control means (416) drives said second buffer (418) to transfer said rewritten data packet from said second buffer (418) through said gate to said selected outgoing line.

Claim 11

A header drive packet switching method for routing a data packet coming through one of said incoming lines and rewriting a header of said data packet according to routing information such as a virtual call number and a line number added to said header of said data packet, comprising the steps of: detecting a free circuit from among a plurality of packet header processing circuits disposed independently from said incoming lines; and controlling, by means of said detected free packet header processing circuit, the routing and header rewriting of said data packet.

Claim 12

A header drive packet switching method for routing a data packet coming through one of said incoming lines and rewriting a header of said data packet according to routing information such as a virtual call number and a line number added to said header of said data packet, comprising the steps of: detecting a free circuit from among a plurality of packet header processing circuits disposed independently from said incoming lines; and controlling, by means of said detected free packet header processing circuit, the routing and header rewriting of said data packet.

Claim 13

A header driven packet switching method as set forth in claim 8, wherein said detecting step comprising the steps of: temporarily storing (215) a data packet coming through an incoming line; scanning (step 301) said plurality of packet header processing circuits to determine a free packet header processing circuit among said plurality of packet header processing circuits; adding an incoming line number to said data packet stored in said first buffer memory means; and transferring said data packet plus said incoming line number from said first buffer to said determined free packet header processing circuit.

Claim 14

A header driven packet switching method as set forth in claim 9, further comprising the steps of: sending information from said packet header processing means to incoming line circuit means, about whether or not each of said packet header processing circuits is free; controlling a competition among process requests from a plurality of said incoming line circuits to determine which incoming line circuit is to be processed; and introducing said data packet from said first buffer to said free packet header processing circuit.

Claim 15

A header driven packet switching method as set forth in claim 9, wherein said controlling step comprises the steps of: temporarily storing said data packet transferred from said first buffer to said free packet header processing circuit; looking up a routing conversion table means to determine an outgoing routing information including the next virtual call number and the outgoing line number; rewriting the header of said data packet with said outgoing information; and generating an outgoing connection request to a selected one of said outgoing line circuits corresponding to said outgoing line number.

Claim 16

A header driven packet switching method as set forth in claim 11, further comprising the steps of: opening a gate, corresponding to the selected outgoing line in said outgoing line circuit, in response to said outgoing connection request; transferring a connection complete signal from said outgoing line circuit to said packet header processing circuit; and transferring said data packet from said packet header processing circuit through said gate to said selected one of said outgoing lines.